Lines Matching refs:tw32
517 #define tw32(reg, val) tp->write32(tp, reg, val)
664 tw32(TG3PCI_MISC_HOST_CTRL,
677 tw32(TG3PCI_MISC_HOST_CTRL,
694 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
696 tw32(HOSTCC_MODE, tp->coal_now);
740 tw32(HOSTCC_MODE, tp->coalesce_mode |
1005 tw32(MAC_PHYCFG2, val);
1011 tw32(MAC_PHYCFG1, val);
1024 tw32(MAC_PHYCFG2, val);
1037 tw32(MAC_PHYCFG1, val);
1058 tw32(MAC_EXT_RGMII_MODE, val);
1444 tw32(MAC_MI_STAT,
1448 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1452 tw32(MAC_TX_LENGTHS,
1457 tw32(MAC_TX_LENGTHS,
1944 tw32(TG3_CPMU_CTRL,
1958 tw32(TG3_CPMU_CTRL, cpmuctrl);
2197 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2198 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2267 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2274 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2301 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2312 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2328 tw32(GRC_EEPROM_ADDR,
2362 tw32(NVRAM_CMD, nvram_cmd);
2431 tw32(NVRAM_ADDR, offset);
2470 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2471 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2477 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2478 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2489 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2540 tw32(TG3PCI_MISC_HOST_CTRL,
2614 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2662 tw32(MAC_LED_CTRL, tp->led_ctrl);
2752 tw32(0x7d00, val);
3056 tw32(MAC_EVENT, 0);
3469 tw32(MAC_TX_AUTO_NEG, 0);
3498 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3513 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4018 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4024 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4058 tw32(MAC_EVENT, 0);
4302 tw32(GRC_MISC_CFG, val);
4307 tw32(MAC_TX_LENGTHS,
4312 tw32(MAC_TX_LENGTHS,
4319 tw32(HOSTCC_STAT_COAL_TICKS,
4322 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4333 tw32(PCIE_PWR_MGMT_THRESH, val);
6553 tw32(FTQ_RESET, 0xffffffff);
6554 tw32(FTQ_RESET, 0x00000000);
6845 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6876 tw32(GRC_FASTBOOT_PC, 0);
6905 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6917 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6920 tw32(GRC_MISC_CFG, (1 << 29));
6926 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6927 tw32(GRC_VCPU_EXT_CTRL,
6936 tw32(GRC_MISC_CFG, val);
7015 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7019 tw32(0x5000, 0x400);
7022 tw32(GRC_MODE, tp->grc_mode);
7027 tw32(0xc4, val | (1 << 15));
7035 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7067 tw32(0x7c00, val | (1 << 25));
7145 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7150 tw32(offset + CPU_STATE, 0xffffffff);
7151 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7156 tw32(offset + CPU_STATE, 0xffffffff);
7161 tw32(offset + CPU_STATE, 0xffffffff);
7162 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7176 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7218 tw32(cpu_base + CPU_STATE, 0xffffffff);
7219 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7264 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7270 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7271 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7281 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7329 tw32(cpu_base + CPU_STATE, 0xffffffff);
7335 tw32(cpu_base + CPU_STATE, 0xffffffff);
7336 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7346 tw32(cpu_base + CPU_STATE, 0xffffffff);
7413 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7414 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7415 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7417 tw32(HOSTCC_TXCOL_TICKS, 0);
7418 tw32(HOSTCC_TXMAX_FRAMES, 0);
7419 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7423 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7424 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7425 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7427 tw32(HOSTCC_RXCOL_TICKS, 0);
7428 tw32(HOSTCC_RXMAX_FRAMES, 0);
7429 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7435 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7436 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7441 tw32(HOSTCC_STAT_COAL_TICKS, val);
7448 tw32(reg, ec->rx_coalesce_usecs);
7450 tw32(reg, ec->rx_max_coalesced_frames);
7452 tw32(reg, ec->rx_max_coalesced_frames_irq);
7456 tw32(reg, ec->tx_coalesce_usecs);
7458 tw32(reg, ec->tx_max_coalesced_frames);
7460 tw32(reg, ec->tx_max_coalesced_frames_irq);
7465 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7466 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7467 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7470 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7471 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7472 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7551 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7553 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7575 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7576 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7626 tw32(TG3_CPMU_CTRL, val);
7631 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7636 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7641 tw32(TG3_CPMU_HST_ACC, val);
7648 tw32(PCIE_PWR_MGMT_THRESH, val);
7651 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7653 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7656 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7664 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7667 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7670 tw32(GRC_MODE, grc_mode);
7678 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7681 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7684 tw32(GRC_MODE, grc_mode);
7689 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7707 tw32(TG3PCI_PCISTATE, val);
7718 tw32(TG3PCI_PCISTATE, val);
7725 tw32(TG3PCI_MSI_DATA, val);
7742 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7748 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7765 tw32(GRC_MODE,
7773 tw32(GRC_MISC_CFG, val);
7779 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7781 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7783 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7784 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7785 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7791 tw32(BUFMGR_MB_POOL_ADDR,
7793 tw32(BUFMGR_MB_POOL_SIZE,
7798 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7800 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7802 tw32(BUFMGR_MB_HIGH_WATER,
7805 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7807 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7809 tw32(BUFMGR_MB_HIGH_WATER,
7812 tw32(BUFMGR_DMA_LOW_WATER,
7814 tw32(BUFMGR_DMA_HIGH_WATER,
7817 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7836 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7842 tw32(RCVBDI_STD_THRESH, val);
7861 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7863 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7867 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7872 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7881 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7884 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7886 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7888 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7893 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7896 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7908 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7918 tw32(STD_REPLENISH_LWM, 32);
7919 tw32(JMB_REPLENISH_LWM, 16);
7928 tw32(MAC_RX_MTU_SIZE,
7934 tw32(MAC_TX_LENGTHS,
7940 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7941 tw32(RCVLPC_CONFIG, 0x0181);
7991 tw32(RCVLPC_STATS_ENABLE, val);
7996 tw32(RCVLPC_STATS_ENABLE, val);
7998 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8000 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8001 tw32(SNDDATAI_STATSENAB, 0xffffff);
8002 tw32(SNDDATAI_STATSCTRL,
8007 tw32(HOSTCC_MODE, 0);
8021 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8023 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8025 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8027 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8038 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8040 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8041 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8043 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8099 tw32(MSGINT_MODE, val);
8157 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8159 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8162 tw32(SNDDATAC_MODE,
8165 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8167 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8168 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8169 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8170 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8172 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8176 tw32(SNDBDI_MODE, val);
8177 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8208 tw32(reg, val);
8214 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8215 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8216 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8217 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8218 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8219 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8220 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8221 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8222 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8223 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8241 tw32(MAC_LED_CTRL, tp->led_ctrl);
8243 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8259 tw32(MAC_SERDES_CFG, val);
8262 tw32(MAC_SERDES_CFG, 0x616000);
8285 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8288 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8319 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8320 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8321 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8322 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8333 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8335 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8337 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8339 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8341 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8343 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8345 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8347 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8349 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8351 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8353 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8355 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8357 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8359 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8384 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8452 tw32(GRC_LOCAL_CTRL,
8455 tw32(HOSTCC_MODE, tp->coalesce_mode |
8610 tw32(MSGINT_MODE, val);
8653 tw32(MSGINT_MODE, val);
8824 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8949 tw32(PCIE_TRANSACTION_CFG,
9244 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9245 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9246 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9247 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9298 tw32(MAC_HASH_REG_0, mc_filter[0]);
9299 tw32(MAC_HASH_REG_1, mc_filter[1]);
9300 tw32(MAC_HASH_REG_2, mc_filter[2]);
9301 tw32(MAC_HASH_REG_3, mc_filter[3]);
10063 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10072 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10078 tw32(MAC_LED_CTRL, tp->led_ctrl);
10443 tw32(offset, 0);
10455 tw32(offset, read_mask | write_mask);
10467 tw32(offset, save_val);
10476 tw32(offset, save_val);
10609 tw32(MAC_MODE, mac_mode);
10651 tw32(MAC_MODE, mac_mode);
10667 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10775 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10790 tw32(TG3_CPMU_CTRL,
10799 tw32(TG3_CPMU_CTRL, cpmuctrl);
10802 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11150 tw32(NVRAM_CFG1, nvcfg1);
11256 tw32(NVRAM_CFG1, nvcfg1);
11332 tw32(NVRAM_CFG1, nvcfg1);
11450 tw32(NVRAM_CFG1, nvcfg1);
11523 tw32(NVRAM_CFG1, nvcfg1);
11666 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11669 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11673 tw32(GRC_EEPROM_ADDR, val |
11747 tw32(NVRAM_ADDR, phy_addr);
11766 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11768 tw32(NVRAM_ADDR, phy_addr + j);
11804 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11810 tw32(NVRAM_ADDR, phy_addr);
11867 tw32(NVRAM_WRITE1, 0x406);
11870 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11883 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12005 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12200 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12201 tw32(OTP_CTRL, cmd);
12222 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12227 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12234 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13339 tw32(GRC_MODE, val | tp->grc_mode);
13344 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13743 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13744 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13745 tw32(RDMAC_STATUS, 0);
13746 tw32(WDMAC_STATUS, 0);
13748 tw32(BUFMGR_MODE, 0);
13749 tw32(FTQ_RESET, 0);
13792 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13794 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13888 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13900 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13934 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13971 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14447 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);