Lines Matching refs:TG3_FL_NOT_5705
10268 #define TG3_FL_NOT_5705 0x2
10275 { MAC_MODE, TG3_FL_NOT_5705,
10279 { MAC_STATUS, TG3_FL_NOT_5705,
10293 { MAC_RX_MODE, TG3_FL_NOT_5705,
10307 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10309 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10311 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10313 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10325 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10329 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10333 { HOSTCC_MODE, TG3_FL_NOT_5705,
10337 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10341 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10345 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10349 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10353 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10355 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10357 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10361 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10365 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10367 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10369 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10391 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10393 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10399 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10417 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))