Lines Matching defs:nvcfg1
11143 u32 nvcfg1;
11145 nvcfg1 = tr32(NVRAM_CFG1);
11146 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11149 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11150 tw32(NVRAM_CFG1, nvcfg1);
11155 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11221 u32 nvcfg1;
11223 nvcfg1 = tr32(NVRAM_CFG1);
11226 if (nvcfg1 & (1 << 27))
11229 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11250 tg3_nvram_get_pagesize(tp, nvcfg1);
11255 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11256 tw32(NVRAM_CFG1, nvcfg1);
11262 u32 nvcfg1, protect = 0;
11264 nvcfg1 = tr32(NVRAM_CFG1);
11267 if (nvcfg1 & (1 << 27)) {
11272 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11273 switch (nvcfg1) {
11282 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11283 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11286 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11300 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11304 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11318 u32 nvcfg1;
11320 nvcfg1 = tr32(NVRAM_CFG1);
11322 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11331 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11332 tw32(NVRAM_CFG1, nvcfg1);
11356 u32 nvcfg1, protect = 0;
11358 nvcfg1 = tr32(NVRAM_CFG1);
11361 if (nvcfg1 & (1 << 27)) {
11366 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11367 switch (nvcfg1) {
11400 switch (nvcfg1) {
11438 u32 nvcfg1;
11440 nvcfg1 = tr32(NVRAM_CFG1);
11442 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11449 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11450 tw32(NVRAM_CFG1, nvcfg1);
11463 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11486 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11503 tg3_nvram_get_pagesize(tp, nvcfg1);
11511 u32 nvcfg1;
11513 nvcfg1 = tr32(NVRAM_CFG1);
11515 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11522 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11523 tw32(NVRAM_CFG1, nvcfg1);
11536 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11561 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11578 tg3_nvram_get_pagesize(tp, nvcfg1);