Lines Matching refs:tr
506 struct tc35815_regs __iomem *tr =
510 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
512 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
517 return tc_readl(&tr->MD_Data) & 0xffff;
523 struct tc35815_regs __iomem *tr =
527 tc_writel(val, &tr->MD_Data);
529 &tr->MD_CA);
531 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
549 struct tc35815_regs __iomem *tr =
553 reg = tc_readl(&tr->MAC_Ctl);
555 tc_writel(reg, &tr->MAC_Ctl);
560 tc_writel(reg, &tr->MAC_Ctl);
562 tc_writel(reg, &tr->MAC_Ctl);
570 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
571 &tr->Tx_Ctl);
746 struct tc35815_regs __iomem *tr =
750 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
754 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
755 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
757 data = tc_readl(&tr->PROM_Data);
1211 struct tc35815_regs __iomem *tr =
1217 tc_writel(0, &tr->Int_En);
1218 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1225 struct tc35815_regs __iomem *tr =
1229 dev->name, tc_readl(&tr->Tx_Stat));
1336 struct tc35815_regs __iomem *tr =
1345 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1456 struct tc35815_regs __iomem *tr =
1458 u32 dmactl = tc_readl(&tr->DMA_Ctl);
1462 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1470 (void)tc_readl(&tr->Int_Src); /* flush */
1648 struct tc35815_regs __iomem *tr =
1654 status = tc_readl(&tr->Int_Src);
1658 &tr->Int_Src); /* write to clear */
1663 &tr->Int_Src);
1669 status = tc_readl(&tr->Int_Src);
1676 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1718 struct tc35815_regs __iomem *tr =
1720 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1803 struct tc35815_regs __iomem *tr =
1829 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1871 struct tc35815_regs __iomem *tr =
1875 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1883 struct tc35815_regs __iomem *tr =
1889 saved_addr = tc_readl(&tr->CAM_Adr);
1896 tc_writel(cam_index - 2, &tr->CAM_Adr);
1897 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1899 tc_writel(cam_data, &tr->CAM_Data);
1901 tc_writel(cam_index + 2, &tr->CAM_Adr);
1903 tc_writel(cam_data, &tr->CAM_Data);
1906 tc_writel(cam_index, &tr->CAM_Adr);
1908 tc_writel(cam_data, &tr->CAM_Data);
1910 tc_writel(cam_index + 4, &tr->CAM_Adr);
1911 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1913 tc_writel(cam_data, &tr->CAM_Data);
1916 tc_writel(saved_addr, &tr->CAM_Adr);
1930 struct tc35815_regs __iomem *tr =
1941 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1946 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1952 tc_writel(0, &tr->CAM_Ctl);
1961 tc_writel(ena_bits, &tr->CAM_Ena);
1962 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1964 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1965 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2067 struct tc35815_regs __iomem *tr =
2071 tc_writel(MAC_Reset, &tr->MAC_Ctl);
2074 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2081 tc_writel(0, &tr->MAC_Ctl);
2084 tc_writel(0, &tr->DMA_Ctl);
2085 tc_writel(0, &tr->TxThrsh);
2086 tc_writel(0, &tr->TxPollCtr);
2087 tc_writel(0, &tr->RxFragSize);
2088 tc_writel(0, &tr->Int_En);
2089 tc_writel(0, &tr->FDA_Bas);
2090 tc_writel(0, &tr->FDA_Lim);
2091 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
2092 tc_writel(0, &tr->CAM_Ctl);
2093 tc_writel(0, &tr->Tx_Ctl);
2094 tc_writel(0, &tr->Rx_Ctl);
2095 tc_writel(0, &tr->CAM_Ena);
2096 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
2099 tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2101 tc_writel(i, &tr->CAM_Adr);
2102 tc_writel(0, &tr->CAM_Data);
2104 tc_writel(0, &tr->DMA_Ctl);
2110 struct tc35815_regs __iomem *tr =
2118 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2119 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2123 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2125 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2126 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
2127 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2128 tc_writel(INT_EN_CMD, &tr->Int_En);
2131 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2133 &tr->FDA_Lim);
2139 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
2140 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
2148 tc_writel(txctl, &tr->Tx_Ctl);