Lines Matching refs:pd
99 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
104 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
109 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
113 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
115 return ioread32(pd->base_addr + offset);
119 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
121 iowrite32(value, pd->base_addr + offset);
124 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
127 smsc9420_reg_read(pd, ID_REV);
132 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
137 spin_lock_irqsave(&pd->phy_lock, flags);
140 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
148 smsc9420_reg_write(pd, MII_ACCESS, addr);
152 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
154 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
163 spin_unlock_irqrestore(&pd->phy_lock, flags);
170 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
175 spin_lock_irqsave(&pd->phy_lock, flags);
178 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
184 smsc9420_reg_write(pd, MII_DATA, (u32)val);
189 smsc9420_reg_write(pd, MII_ACCESS, addr);
193 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
204 spin_unlock_irqrestore(&pd->phy_lock, flags);
216 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
220 BUG_ON(!pd);
222 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
227 smsc9420_reg_write(pd, E2P_CMD,
232 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
243 struct smsc9420_pdata *pd = netdev_priv(dev);
245 if (!netif_running(dev) || !pd->phy_dev)
248 return phy_mii_ioctl(pd->phy_dev, ifr, cmd);
254 struct smsc9420_pdata *pd = netdev_priv(dev);
256 if (!pd->phy_dev)
261 return phy_ethtool_gset(pd->phy_dev, cmd);
267 struct smsc9420_pdata *pd = netdev_priv(dev);
269 if (!pd->phy_dev)
272 return phy_ethtool_sset(pd->phy_dev, cmd);
278 struct smsc9420_pdata *pd = netdev_priv(netdev);
281 strcpy(drvinfo->bus_info, pci_name(pd->pdev));
287 struct smsc9420_pdata *pd = netdev_priv(netdev);
288 return pd->msg_enable;
293 struct smsc9420_pdata *pd = netdev_priv(netdev);
294 pd->msg_enable = data;
299 struct smsc9420_pdata *pd = netdev_priv(netdev);
301 if (!pd->phy_dev)
304 return phy_start_aneg(pd->phy_dev);
317 struct smsc9420_pdata *pd = netdev_priv(dev);
318 struct phy_device *phy_dev = pd->phy_dev;
322 regs->version = smsc9420_reg_read(pd, ID_REV);
324 data[j++] = smsc9420_reg_read(pd, i);
334 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
336 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
338 smsc9420_reg_write(pd, GPIO_CFG, temp);
342 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
348 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
354 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
358 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
374 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
381 ret = smsc9420_eeprom_send_cmd(pd, op);
384 data[address] = smsc9420_reg_read(pd, E2P_DATA);
389 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
396 ret = smsc9420_eeprom_send_cmd(pd, op);
400 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
401 ret = smsc9420_eeprom_send_cmd(pd, op);
415 struct smsc9420_pdata *pd = netdev_priv(dev);
419 smsc9420_eeprom_enable_access(pd);
423 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
439 struct smsc9420_pdata *pd = netdev_priv(dev);
445 smsc9420_eeprom_enable_access(pd);
446 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
447 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
448 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
474 struct smsc9420_pdata *pd = netdev_priv(dev);
480 smsc9420_reg_write(pd, ADDRH, mac_high16);
481 smsc9420_reg_write(pd, ADDRL, mac_low32);
486 struct smsc9420_pdata *pd = netdev_priv(dev);
495 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
496 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
517 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
523 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
525 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
529 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
538 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
541 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
543 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
544 smsc9420_pci_flush_write(pd);
547 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
548 smsc9420_reg_write(pd, MAC_CR, mac_cr);
549 smsc9420_pci_flush_write(pd);
552 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
556 BUG_ON(!pd->tx_ring);
558 if (!pd->tx_buffers)
562 struct sk_buff *skb = pd->tx_buffers[i].skb;
565 BUG_ON(!pd->tx_buffers[i].mapping);
566 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
571 pd->tx_ring[i].status = 0;
572 pd->tx_ring[i].length = 0;
573 pd->tx_ring[i].buffer1 = 0;
574 pd->tx_ring[i].buffer2 = 0;
578 kfree(pd->tx_buffers);
579 pd->tx_buffers = NULL;
581 pd->tx_ring_head = 0;
582 pd->tx_ring_tail = 0;
585 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
589 BUG_ON(!pd->rx_ring);
591 if (!pd->rx_buffers)
595 if (pd->rx_buffers[i].skb)
596 dev_kfree_skb_any(pd->rx_buffers[i].skb);
598 if (pd->rx_buffers[i].mapping)
599 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
602 pd->rx_ring[i].status = 0;
603 pd->rx_ring[i].length = 0;
604 pd->rx_ring[i].buffer1 = 0;
605 pd->rx_ring[i].buffer2 = 0;
609 kfree(pd->rx_buffers);
610 pd->rx_buffers = NULL;
612 pd->rx_ring_head = 0;
613 pd->rx_ring_tail = 0;
616 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
622 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
624 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
625 smsc9420_pci_flush_write(pd);
628 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
629 smsc9420_reg_write(pd, MAC_CR, mac_cr);
630 smsc9420_pci_flush_write(pd);
633 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
635 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
636 smsc9420_pci_flush_write(pd);
640 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
649 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
654 struct smsc9420_pdata *pd = dev_id;
659 BUG_ON(!pd);
660 BUG_ON(!pd->base_addr);
662 int_cfg = smsc9420_reg_read(pd, INT_CFG);
669 int_sts = smsc9420_reg_read(pd, INT_STAT);
672 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
677 netif_wake_queue(pd->dev);
682 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
684 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
685 smsc9420_pci_flush_write(pd);
688 napi_schedule(&pd->napi);
692 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
699 spin_lock_irqsave(&pd->int_lock, flags);
700 int_ctl = smsc9420_reg_read(pd, INT_CTL);
702 smsc9420_reg_write(pd, INT_CTL, int_ctl);
703 spin_unlock_irqrestore(&pd->int_lock, flags);
705 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
706 pd->software_irq_signal = true;
713 smsc9420_pci_flush_write(pd);
727 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
729 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
730 smsc9420_reg_read(pd, BUS_MODE);
732 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
738 struct smsc9420_pdata *pd = netdev_priv(dev);
742 BUG_ON(!pd);
743 BUG_ON(!pd->phy_dev);
746 spin_lock_irqsave(&pd->int_lock, flags);
747 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
748 smsc9420_reg_write(pd, INT_CFG, int_cfg);
749 spin_unlock_irqrestore(&pd->int_lock, flags);
752 napi_disable(&pd->napi);
754 smsc9420_stop_tx(pd);
755 smsc9420_free_tx_ring(pd);
757 smsc9420_stop_rx(pd);
758 smsc9420_free_rx_ring(pd);
760 free_irq(dev->irq, pd);
762 smsc9420_dmac_soft_reset(pd);
764 phy_stop(pd->phy_dev);
766 phy_disconnect(pd->phy_dev);
767 pd->phy_dev = NULL;
768 mdiobus_unregister(pd->mii_bus);
769 mdiobus_free(pd->mii_bus);
798 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
801 struct net_device *dev = pd->dev;
809 if (pd->rx_csum)
815 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
817 pd->rx_buffers[index].mapping = 0;
819 skb = pd->rx_buffers[index].skb;
820 pd->rx_buffers[index].skb = NULL;
822 if (pd->rx_csum) {
837 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
839 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
842 BUG_ON(pd->rx_buffers[index].skb);
843 BUG_ON(pd->rx_buffers[index].mapping);
850 skb->dev = pd->dev;
852 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
854 if (pci_dma_mapping_error(pd->pdev, mapping)) {
860 pd->rx_buffers[index].skb = skb;
861 pd->rx_buffers[index].mapping = mapping;
862 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
863 pd->rx_ring[index].status = RDES0_OWN_;
869 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
871 while (pd->rx_ring_tail != pd->rx_ring_head) {
872 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
875 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
881 struct smsc9420_pdata *pd =
883 struct net_device *dev = pd->dev;
889 status = pd->rx_ring[pd->rx_ring_head].status;
896 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
897 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
898 smsc9420_alloc_new_rx_buffers(pd);
901 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
906 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
907 smsc9420_pci_flush_write(pd);
910 napi_complete(&pd->napi);
913 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
915 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
916 smsc9420_pci_flush_write(pd);
952 struct smsc9420_pdata *pd = netdev_priv(dev);
954 while (pd->tx_ring_tail != pd->tx_ring_head) {
955 int index = pd->tx_ring_tail;
959 status = pd->tx_ring[index].status;
960 length = pd->tx_ring[index].length;
968 BUG_ON(!pd->tx_buffers[index].skb);
969 BUG_ON(!pd->tx_buffers[index].mapping);
971 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
972 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
973 pd->tx_buffers[index].mapping = 0;
975 dev_kfree_skb_any(pd->tx_buffers[index].skb);
976 pd->tx_buffers[index].skb = NULL;
978 pd->tx_ring[index].buffer1 = 0;
981 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
988 struct smsc9420_pdata *pd = netdev_priv(dev);
990 int index = pd->tx_ring_head;
993 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
998 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
999 BUG_ON(pd->tx_buffers[index].skb);
1000 BUG_ON(pd->tx_buffers[index].mapping);
1002 mapping = pci_map_single(pd->pdev, skb->data,
1004 if (pci_dma_mapping_error(pd->pdev, mapping)) {
1009 pd->tx_buffers[index].skb = skb;
1010 pd->tx_buffers[index].mapping = mapping;
1015 netif_stop_queue(pd->dev);
1022 pd->tx_ring[index].buffer1 = mapping;
1023 pd->tx_ring[index].length = tmp_desc1;
1027 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
1030 pd->tx_ring[index].status = TDES0_OWN_;
1034 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
1035 smsc9420_pci_flush_write(pd);
1042 struct smsc9420_pdata *pd = netdev_priv(dev);
1043 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
1051 struct smsc9420_pdata *pd = netdev_priv(dev);
1052 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1079 smsc9420_reg_write(pd, HASHH, hash_hi);
1080 smsc9420_reg_write(pd, HASHL, hash_lo);
1087 smsc9420_reg_write(pd, HASHH, 0);
1088 smsc9420_reg_write(pd, HASHL, 0);
1095 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1096 smsc9420_pci_flush_write(pd);
1099 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1101 struct phy_device *phy_dev = pd->phy_dev;
1122 smsc9420_reg_write(pd, FLOW, flow);
1129 struct smsc9420_pdata *pd = netdev_priv(dev);
1130 struct phy_device *phy_dev = pd->phy_dev;
1133 if (phy_dev->duplex != pd->last_duplex) {
1134 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1142 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1144 smsc9420_phy_update_flowcontrol(pd);
1145 pd->last_duplex = phy_dev->duplex;
1149 if (carrier != pd->last_carrier) {
1154 pd->last_carrier = carrier;
1160 struct smsc9420_pdata *pd = netdev_priv(dev);
1163 BUG_ON(pd->phy_dev);
1166 if (!pd->mii_bus->phy_map[1]) {
1171 phydev = pd->mii_bus->phy_map[1];
1191 pd->phy_dev = phydev;
1192 pd->last_duplex = -1;
1193 pd->last_carrier = -1;
1200 struct smsc9420_pdata *pd = netdev_priv(dev);
1203 pd->mii_bus = mdiobus_alloc();
1204 if (!pd->mii_bus) {
1208 pd->mii_bus->name = DRV_MDIONAME;
1209 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1210 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1211 pd->mii_bus->priv = pd;
1212 pd->mii_bus->read = smsc9420_mii_read;
1213 pd->mii_bus->write = smsc9420_mii_write;
1214 pd->mii_bus->irq = pd->phy_irq;
1216 pd->mii_bus->irq[i] = PHY_POLL;
1219 pd->mii_bus->phy_mask = ~(1 << 1);
1221 if (mdiobus_register(pd->mii_bus)) {
1234 mdiobus_unregister(pd->mii_bus);
1236 mdiobus_free(pd->mii_bus);
1241 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1245 BUG_ON(!pd->tx_ring);
1247 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1249 if (!pd->tx_buffers) {
1256 pd->tx_buffers[i].skb = NULL;
1257 pd->tx_buffers[i].mapping = 0;
1258 pd->tx_ring[i].status = 0;
1259 pd->tx_ring[i].length = 0;
1260 pd->tx_ring[i].buffer1 = 0;
1261 pd->tx_ring[i].buffer2 = 0;
1263 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1266 pd->tx_ring_head = 0;
1267 pd->tx_ring_tail = 0;
1269 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1270 smsc9420_pci_flush_write(pd);
1275 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1279 BUG_ON(!pd->rx_ring);
1281 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1283 if (pd->rx_buffers == NULL) {
1290 pd->rx_ring[i].status = 0;
1291 pd->rx_ring[i].length = PKT_BUF_SZ;
1292 pd->rx_ring[i].buffer2 = 0;
1293 pd->rx_buffers[i].skb = NULL;
1294 pd->rx_buffers[i].mapping = 0;
1296 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1300 if (smsc9420_alloc_rx_buffer(pd, i)) {
1306 pd->rx_ring_head = 0;
1307 pd->rx_ring_tail = 0;
1309 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1310 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1));
1312 if (pd->rx_csum) {
1314 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1315 smsc9420_reg_write(pd, COE_CR, coe);
1319 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1320 smsc9420_pci_flush_write(pd);
1325 smsc9420_free_rx_ring(pd);
1332 struct smsc9420_pdata *pd;
1338 pd = netdev_priv(dev);
1339 BUG_ON(!pd);
1350 spin_lock_irqsave(&pd->int_lock, flags);
1351 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1352 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1353 smsc9420_reg_write(pd, INT_CTL, 0);
1354 spin_unlock_irqrestore(&pd->int_lock, flags);
1355 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1356 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1357 smsc9420_pci_flush_write(pd);
1360 DRV_NAME, pd)) {
1366 smsc9420_dmac_soft_reset(pd);
1369 smsc9420_reg_write(pd, MAC_CR, 0);
1374 smsc9420_reg_write(pd, GPIO_CFG,
1383 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1385 smsc9420_pci_flush_write(pd);
1388 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1390 smsc9420_reg_write(pd, DMAC_CONTROL,
1393 smsc9420_pci_flush_write(pd);
1397 pd->software_irq_signal = false;
1399 spin_lock_irqsave(&pd->int_lock, flags);
1401 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1404 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1407 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1408 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1409 spin_unlock_irqrestore(&pd->int_lock, flags);
1410 smsc9420_pci_flush_write(pd);
1414 if (pd->software_irq_signal)
1420 spin_lock_irqsave(&pd->int_lock, flags);
1421 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1422 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1423 spin_unlock_irqrestore(&pd->int_lock, flags);
1425 if (!pd->software_irq_signal) {
1433 result = smsc9420_alloc_tx_ring(pd);
1440 result = smsc9420_alloc_rx_ring(pd);
1455 phy_start(pd->phy_dev);
1457 napi_enable(&pd->napi);
1460 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1461 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1463 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1465 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1466 smsc9420_pci_flush_write(pd);
1468 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1471 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1472 smsc9420_pci_flush_write(pd);
1476 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1479 spin_lock_irqsave(&pd->int_lock, flags);
1480 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1481 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1482 spin_unlock_irqrestore(&pd->int_lock, flags);
1487 smsc9420_free_rx_ring(pd);
1489 smsc9420_free_tx_ring(pd);
1491 free_irq(dev->irq, pd);
1501 struct smsc9420_pdata *pd = netdev_priv(dev);
1506 spin_lock_irqsave(&pd->int_lock, flags);
1507 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1508 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1509 spin_unlock_irqrestore(&pd->int_lock, flags);
1513 smsc9420_stop_tx(pd);
1514 smsc9420_free_tx_ring(pd);
1516 napi_disable(&pd->napi);
1517 smsc9420_stop_rx(pd);
1518 smsc9420_free_rx_ring(pd);
1520 free_irq(dev->irq, pd);
1536 struct smsc9420_pdata *pd = netdev_priv(dev);
1579 struct smsc9420_pdata *pd;
1595 dev = alloc_etherdev(sizeof(*pd));
1630 pd = netdev_priv(dev);
1633 pd->rx_ring = pci_alloc_consistent(pdev,
1636 &pd->rx_dma_addr);
1638 if (!pd->rx_ring)
1642 pd->tx_ring = (struct smsc9420_dma_desc *)
1643 (pd->rx_ring + RX_RING_SIZE);
1644 pd->tx_dma_addr = pd->rx_dma_addr +
1647 pd->pdev = pdev;
1648 pd->dev = dev;
1649 pd->base_addr = virt_addr;
1650 pd->msg_enable = smsc_debug;
1651 pd->rx_csum = true;
1655 id_rev = smsc9420_reg_read(pd, ID_REV);
1666 smsc9420_dmac_soft_reset(pd);
1667 smsc9420_eeprom_reload(pd);
1674 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1684 spin_lock_init(&pd->int_lock);
1685 spin_lock_init(&pd->phy_lock);
1693 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1709 struct smsc9420_pdata *pd;
1717 pd = netdev_priv(dev);
1721 BUG_ON(pd->tx_buffers);
1722 BUG_ON(pd->rx_buffers);
1724 BUG_ON(!pd->tx_ring);
1725 BUG_ON(!pd->rx_ring);
1728 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1730 iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET);