Lines Matching refs:sky2_write32
225 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
257 sky2_write32(hw, B2_GP_IO, reg);
809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
812 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
815 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
817 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
913 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
967 sky2_write32(hw, RB_ADDR(q, RB_START), start);
968 sky2_write32(hw, RB_ADDR(q, RB_END), end);
969 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
970 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
979 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
980 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
983 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
984 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
999 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1000 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1001 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1002 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1011 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1012 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1013 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1014 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1016 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1197 sky2_write32(sky2->hw,
1213 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1222 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1226 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1229 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1232 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1262 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1265 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1327 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1329 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1332 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1334 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1449 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1455 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1473 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1476 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1491 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1500 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1610 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1647 sky2_write32(hw, B0_IMSK, imask);
1923 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1924 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1927 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1931 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1934 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1948 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1951 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1967 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1968 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1969 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1997 sky2_write32(hw, B0_IMSK,
2206 sky2_write32(hw, B0_IMSK, imask);
2265 sky2_write32(hw, B0_IMSK, 0);
2298 sky2_write32(hw, B0_IMSK, imask);
2558 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2663 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2702 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2708 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2743 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2794 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
3094 sky2_write32(hw, CPU_WDOG, 0);
3105 sky2_write32(hw, CPU_WDOG, 0);
3126 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3162 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3183 sky2_write32(hw, B0_IMSK, msk);
3195 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3199 sky2_write32(hw, B2_I2C_IRQ, 1);
3206 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3234 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3242 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3243 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3245 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3246 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3260 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3261 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3262 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3265 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3310 sky2_write32(hw, B0_IMSK, 0);
3345 sky2_write32(hw, B0_IMSK, imask);
3567 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3901 sky2_write32(hw, STAT_TX_TIMER_INI,
3910 sky2_write32(hw, STAT_LEV_TIMER_INI,
3919 sky2_write32(hw, STAT_ISR_TIMER_INI,
4608 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4621 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4643 sky2_write32(hw, B0_IMSK, 0);
4810 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4878 sky2_write32(hw, B0_IMSK, 0);