Lines Matching refs:hw
104 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
105 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
108 static void yukon_init(struct skge_hw *hw, int port);
109 static void genesis_mac_init(struct skge_hw *hw, int port);
135 const void __iomem *io = skge->hw->regs;
146 static u32 wol_supported(const struct skge_hw *hw)
148 if (hw->chip_id == CHIP_ID_GENESIS)
151 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
159 struct skge_hw *hw = skge->hw;
163 skge_write16(hw, B0_CTST, CS_RST_CLR);
164 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
167 skge_write8(hw, B0_POWER_CTRL,
171 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
172 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
173 u32 reg = skge_read32(hw, B2_GP_IO);
176 skge_write32(hw, B2_GP_IO, reg);
179 skge_write32(hw, SK_REG(port, GPHY_CTRL),
184 skge_write32(hw, SK_REG(port, GPHY_CTRL),
189 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
192 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
196 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
197 gm_phy_write(hw, port, PHY_MARV_CTRL,
203 gma_write16(hw, port, GM_GP_CTRL,
208 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
212 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
225 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
228 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
235 wol->supported = wol_supported(skge->hw);
242 struct skge_hw *hw = skge->hw;
244 if ((wol->wolopts & ~wol_supported(hw)) ||
245 !device_can_wakeup(&hw->pdev->dev))
250 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
258 static u32 skge_supported_modes(const struct skge_hw *hw)
262 if (hw->copper) {
272 if (hw->chip_id == CHIP_ID_GENESIS)
278 else if (hw->chip_id == CHIP_ID_YUKON)
293 struct skge_hw *hw = skge->hw;
296 ecmd->supported = skge_supported_modes(hw);
298 if (hw->copper) {
300 ecmd->phy_address = hw->phy_addr;
314 const struct skge_hw *hw = skge->hw;
315 u32 supported = skge_supported_modes(hw);
385 strcpy(info->bus_info, pci_name(skge->hw->pdev));
434 if (skge->hw->chip_id == CHIP_ID_GENESIS)
449 if (skge->hw->chip_id == CHIP_ID_GENESIS)
543 struct skge_hw *hw = skge->hw;
545 if (hw->chip_id == CHIP_ID_GENESIS && data)
553 struct skge_hw *hw = skge->hw;
555 if (hw->chip_id == CHIP_ID_GENESIS && data)
573 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
628 static inline u32 hwkhz(const struct skge_hw *hw)
630 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
634 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
636 return (ticks * 1000) / hwkhz(hw);
640 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
642 return hwkhz(hw) * usec / 1000;
649 struct skge_hw *hw = skge->hw;
655 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
656 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
657 u32 msk = skge_read32(hw, B2_IRQM_MSK);
673 struct skge_hw *hw = skge->hw;
675 u32 msk = skge_read32(hw, B2_IRQM_MSK);
698 skge_write32(hw, B2_IRQM_MSK, msk);
700 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
702 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
703 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
711 struct skge_hw *hw = skge->hw;
714 spin_lock_bh(&hw->phy_lock);
715 if (hw->chip_id == CHIP_ID_GENESIS) {
718 if (hw->phy_type == SK_PHY_BCOM)
719 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
721 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
722 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
724 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
725 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
726 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
730 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
731 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
733 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
734 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
739 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
740 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
741 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
743 if (hw->phy_type == SK_PHY_BCOM)
744 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
746 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
747 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
748 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
755 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
756 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
764 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
770 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
776 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
777 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
785 spin_unlock_bh(&hw->phy_lock);
820 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
853 struct pci_dev *pdev = skge->hw->pdev;
879 struct pci_dev *pdev = skge->hw->pdev;
974 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
1012 struct skge_hw *hw = skge->hw;
1021 pci_unmap_single(hw->pdev,
1077 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1092 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1100 static void xm_link_down(struct skge_hw *hw, int port)
1102 struct net_device *dev = hw->dev[port];
1105 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1111 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1115 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1116 *val = xm_read16(hw, port, XM_PHY_DATA);
1118 if (hw->phy_type == SK_PHY_XMAC)
1122 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1129 *val = xm_read16(hw, port, XM_PHY_DATA);
1134 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1137 if (__xm_phy_read(hw, port, reg, &v))
1138 pr_warning("%s: phy read timed out\n", hw->dev[port]->name);
1142 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1146 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1148 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1155 xm_write16(hw, port, XM_PHY_DATA, val);
1157 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1164 static void genesis_init(struct skge_hw *hw)
1167 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1168 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1171 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1174 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1175 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1176 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1177 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1179 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1180 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1181 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1182 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1185 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1186 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1187 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1188 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1189 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1192 static void genesis_reset(struct skge_hw *hw, int port)
1197 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1200 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1201 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1202 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1203 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1204 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1207 if (hw->phy_type == SK_PHY_BCOM)
1208 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1210 xm_outhash(hw, port, XM_HSM, zero);
1213 reg = xm_read32(hw, port, XM_MODE);
1214 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1215 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1237 static void bcom_check_link(struct skge_hw *hw, int port)
1239 struct net_device *dev = hw->dev[port];
1244 xm_phy_read(hw, port, PHY_BCOM_STAT);
1245 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1248 xm_link_down(hw, port);
1258 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1264 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1305 struct skge_hw *hw = skge->hw;
1324 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1327 r = xm_read16(hw, port, XM_MMU_CMD);
1329 xm_write16(hw, port, XM_MMU_CMD, r);
1334 xm_phy_write(hw, port,
1340 xm_phy_write(hw, port,
1345 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1347 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1350 xm_read16(hw, port, XM_ISRC);
1361 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1368 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1372 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1376 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1377 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1384 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1385 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1388 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1393 struct skge_hw *hw = skge->hw;
1405 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1419 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1428 struct skge_hw *hw = skge->hw;
1433 xm_phy_read(hw, port, PHY_XMAC_STAT);
1434 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1437 xm_link_down(hw, port);
1447 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1453 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1502 struct skge_hw *hw = skge->hw;
1510 spin_lock_irqsave(&hw->phy_lock, flags);
1517 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1523 u16 msk = xm_read16(hw, port, XM_IMSK);
1525 xm_write16(hw, port, XM_IMSK, msk);
1526 xm_read16(hw, port, XM_ISRC);
1532 spin_unlock_irqrestore(&hw->phy_lock, flags);
1535 static void genesis_mac_init(struct skge_hw *hw, int port)
1537 struct net_device *dev = hw->dev[port];
1539 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1545 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1547 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1556 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1563 if (hw->phy_type != SK_PHY_XMAC) {
1565 r = skge_read32(hw, B2_GP_IO);
1571 skge_write32(hw, B2_GP_IO, r);
1574 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1578 switch (hw->phy_type) {
1584 bcom_check_link(hw, port);
1588 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1592 xm_outaddr(hw, port, XM_EXM(i), zero);
1595 xm_write16(hw, port, XM_STAT_CMD,
1598 xm_write16(hw, port, XM_STAT_CMD,
1602 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1617 xm_write16(hw, port, XM_RX_CMD, r);
1620 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1623 if (hw->ports > 1 && jumbo)
1624 xm_write16(hw, port, XM_TX_THR, 1020);
1626 xm_write16(hw, port, XM_TX_THR, 512);
1642 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1650 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1657 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1660 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1663 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1664 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1665 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1666 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1668 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1669 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1670 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1671 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1674 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1675 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1676 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1679 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1680 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1681 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1685 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1688 skge_write16(hw, B3_PA_CTRL,
1695 struct skge_hw *hw = skge->hw;
1701 cmd = xm_read16(hw, port, XM_MMU_CMD);
1703 xm_write16(hw, port, XM_MMU_CMD, cmd);
1705 genesis_reset(hw, port);
1708 skge_write16(hw, B3_PA_CTRL,
1712 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1714 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1715 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1720 if (hw->phy_type != SK_PHY_XMAC) {
1721 u32 reg = skge_read32(hw, B2_GP_IO);
1729 skge_write32(hw, B2_GP_IO, reg);
1730 skge_read32(hw, B2_GP_IO);
1733 xm_write16(hw, port, XM_MMU_CMD,
1734 xm_read16(hw, port, XM_MMU_CMD)
1737 xm_read16(hw, port, XM_MMU_CMD);
1743 struct skge_hw *hw = skge->hw;
1748 xm_write16(hw, port,
1752 while (xm_read16(hw, port, XM_STAT_CMD)
1760 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1761 | xm_read32(hw, port, XM_TXO_OK_LO);
1762 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1763 | xm_read32(hw, port, XM_RXO_OK_LO);
1766 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1769 static void genesis_mac_intr(struct skge_hw *hw, int port)
1771 struct net_device *dev = hw->dev[port];
1773 u16 status = xm_read16(hw, port, XM_ISRC);
1778 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1779 xm_link_down(hw, port);
1784 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1791 struct skge_hw *hw = skge->hw;
1796 cmd = xm_read16(hw, port, XM_MMU_CMD);
1810 xm_write16(hw, port, XM_MMU_CMD, cmd);
1812 mode = xm_read32(hw, port, XM_MODE);
1826 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1829 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1838 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1841 xm_write32(hw, port, XM_MODE, mode);
1844 msk = xm_read16(hw, port, XM_IMSK);
1846 xm_write16(hw, port, XM_IMSK, msk);
1848 xm_read16(hw, port, XM_ISRC);
1851 cmd = xm_read16(hw, port, XM_MMU_CMD);
1852 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1855 if (hw->phy_type == SK_PHY_BCOM) {
1856 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1857 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1859 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1863 xm_write16(hw, port, XM_MMU_CMD,
1871 struct skge_hw *hw = skge->hw;
1875 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1881 hw->dev[port]->name);
1884 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1885 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1887 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1892 bcom_check_link(hw, port);
1896 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1900 gma_write16(hw, port, GM_SMI_DATA, val);
1901 gma_write16(hw, port, GM_SMI_CTRL,
1902 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1906 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1910 pr_warning("%s: phy write timeout\n", hw->dev[port]->name);
1914 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1918 gma_write16(hw, port, GM_SMI_CTRL,
1919 GM_SMI_CT_PHY_AD(hw->phy_addr)
1924 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1930 *val = gma_read16(hw, port, GM_SMI_DATA);
1934 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1937 if (__gm_phy_read(hw, port, reg, &v))
1938 pr_warning("%s: phy read timeout\n", hw->dev[port]->name);
1943 static void yukon_init(struct skge_hw *hw, int port)
1945 struct skge_port *skge = netdev_priv(hw->dev[port]);
1949 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1957 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1960 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1965 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1972 if (hw->copper) {
2018 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2020 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2021 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2025 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2027 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2030 static void yukon_reset(struct skge_hw *hw, int port)
2032 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2033 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2034 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2035 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2036 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2038 gma_write16(hw, port, GM_RX_CTRL,
2039 gma_read16(hw, port, GM_RX_CTRL)
2044 static int is_yukon_lite_a0(struct skge_hw *hw)
2049 if (hw->chip_id != CHIP_ID_YUKON)
2052 reg = skge_read32(hw, B2_FAR);
2053 skge_write8(hw, B2_FAR + 3, 0xff);
2054 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2055 skge_write32(hw, B2_FAR, reg);
2059 static void yukon_mac_init(struct skge_hw *hw, int port)
2061 struct skge_port *skge = netdev_priv(hw->dev[port]);
2064 const u8 *addr = hw->dev[port]->dev_addr;
2067 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2068 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2069 reg = skge_read32(hw, B2_GP_IO);
2071 skge_write32(hw, B2_GP_IO, reg);
2075 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2076 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2079 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2080 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2081 reg = skge_read32(hw, B2_GP_IO);
2084 skge_write32(hw, B2_GP_IO, reg);
2090 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2093 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2094 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2095 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2099 gma_write16(hw, port, GM_GP_CTRL,
2100 gma_read16(hw, port, GM_GP_CTRL) | reg);
2123 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2136 gma_write16(hw, port, GM_GP_CTRL, reg);
2137 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2139 yukon_init(hw, port);
2142 reg = gma_read16(hw, port, GM_PHY_ADDR);
2143 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2146 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2147 gma_write16(hw, port, GM_PHY_ADDR, reg);
2150 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2153 gma_write16(hw, port, GM_RX_CTRL,
2157 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2160 gma_write16(hw, port, GM_TX_PARAM,
2170 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2173 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2176 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2178 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2181 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2182 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2183 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2188 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2192 if (is_yukon_lite_a0(hw))
2195 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2196 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2202 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2205 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2206 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2210 static void yukon_suspend(struct skge_hw *hw, int port)
2214 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2216 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2218 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2220 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2223 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2225 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2230 struct skge_hw *hw = skge->hw;
2233 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2234 yukon_reset(hw, port);
2236 gma_write16(hw, port, GM_GP_CTRL,
2237 gma_read16(hw, port, GM_GP_CTRL)
2239 gma_read16(hw, port, GM_GP_CTRL);
2241 yukon_suspend(hw, port);
2244 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2245 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2250 struct skge_hw *hw = skge->hw;
2254 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2255 | gma_read32(hw, port, GM_TXO_OK_LO);
2256 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2257 | gma_read32(hw, port, GM_RXO_OK_LO);
2260 data[i] = gma_read32(hw, port,
2264 static void yukon_mac_intr(struct skge_hw *hw, int port)
2266 struct net_device *dev = hw->dev[port];
2268 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2275 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2280 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2285 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2299 struct skge_hw *hw = skge->hw;
2304 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2306 reg = gma_read16(hw, port, GM_GP_CTRL);
2312 gma_write16(hw, port, GM_GP_CTRL, reg);
2314 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2320 struct skge_hw *hw = skge->hw;
2324 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2326 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2329 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2332 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2337 yukon_init(hw, port);
2342 struct skge_hw *hw = skge->hw;
2347 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2348 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2354 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2360 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2372 skge->speed = yukon_speed(hw, phystat);
2391 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2393 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2399 skge->speed = yukon_speed(hw, phystat);
2417 struct skge_hw *hw = skge->hw;
2419 struct net_device *dev = hw->dev[port];
2424 spin_lock_bh(&hw->phy_lock);
2425 if (hw->chip_id == CHIP_ID_GENESIS) {
2426 genesis_reset(hw, port);
2427 genesis_mac_init(hw, port);
2429 yukon_reset(hw, port);
2430 yukon_init(hw, port);
2432 spin_unlock_bh(&hw->phy_lock);
2442 struct skge_hw *hw = skge->hw;
2450 data->phy_id = hw->phy_addr;
2455 spin_lock_bh(&hw->phy_lock);
2456 if (hw->chip_id == CHIP_ID_GENESIS)
2457 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2459 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2460 spin_unlock_bh(&hw->phy_lock);
2466 spin_lock_bh(&hw->phy_lock);
2467 if (hw->chip_id == CHIP_ID_GENESIS)
2468 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2471 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2473 spin_unlock_bh(&hw->phy_lock);
2479 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2487 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2488 skge_write32(hw, RB_ADDR(q, RB_START), start);
2489 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2490 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2491 skge_write32(hw, RB_ADDR(q, RB_END), end);
2495 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2497 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2503 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2506 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2513 struct skge_hw *hw = skge->hw;
2518 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2521 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2522 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2523 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2524 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2530 struct skge_hw *hw = skge->hw;
2550 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2557 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2578 spin_lock_bh(&hw->phy_lock);
2579 if (hw->chip_id == CHIP_ID_GENESIS)
2580 genesis_mac_init(hw, port);
2582 yukon_mac_init(hw, port);
2583 spin_unlock_bh(&hw->phy_lock);
2586 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2587 ram_addr = hw->ram_offset + 2 * chunk * port;
2589 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2593 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2598 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2601 spin_lock_irq(&hw->hw_lock);
2602 hw->intr_mask |= portmask[port];
2603 skge_write32(hw, B0_IMSK, hw->intr_mask);
2604 spin_unlock_irq(&hw->hw_lock);
2613 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2620 static void skge_rx_stop(struct skge_hw *hw, int port)
2622 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2623 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2625 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2631 struct skge_hw *hw = skge->hw;
2641 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2647 spin_lock_irq(&hw->hw_lock);
2648 hw->intr_mask &= ~portmask[port];
2649 skge_write32(hw, B0_IMSK, hw->intr_mask);
2650 spin_unlock_irq(&hw->hw_lock);
2652 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2653 if (hw->chip_id == CHIP_ID_GENESIS)
2659 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2660 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2665 skge_write8(hw, SK_REG(port, TXA_CTRL),
2669 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2670 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2673 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2674 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2677 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2679 skge_rx_stop(hw, port);
2681 if (hw->chip_id == CHIP_ID_GENESIS) {
2682 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2683 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2685 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2686 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2699 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2715 struct skge_hw *hw = skge->hw;
2733 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2747 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2767 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2789 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2811 struct pci_dev *pdev = skge->hw->pdev;
2852 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2894 struct skge_hw *hw = skge->hw;
2900 mode = xm_read32(hw, port, XM_MODE);
2920 xm_write32(hw, port, XM_MODE, mode);
2921 xm_outhash(hw, port, XM_HSM, filter);
2933 struct skge_hw *hw = skge->hw;
2943 reg = gma_read16(hw, port, GM_RX_CTRL);
2963 gma_write16(hw, port, GM_MC_ADDR_H1,
2965 gma_write16(hw, port, GM_MC_ADDR_H2,
2967 gma_write16(hw, port, GM_MC_ADDR_H3,
2969 gma_write16(hw, port, GM_MC_ADDR_H4,
2972 gma_write16(hw, port, GM_RX_CTRL, reg);
2975 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2977 if (hw->chip_id == CHIP_ID_GENESIS)
2983 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2985 if (hw->chip_id == CHIP_ID_GENESIS)
2995 struct skge_hw *hw = skge->hw;
2997 if (hw->chip_id == CHIP_ID_GENESIS)
3026 if (bad_phy_status(skge->hw, status))
3029 if (phy_length(skge->hw, status) != len)
3037 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3041 pci_dma_sync_single_for_device(skge->hw->pdev,
3052 pci_unmap_single(skge->hw->pdev,
3076 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3104 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3135 struct skge_hw *hw = skge->hw;
3142 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3165 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3170 spin_lock_irqsave(&hw->hw_lock, flags);
3172 hw->intr_mask |= napimask[skge->port];
3173 skge_write32(hw, B0_IMSK, hw->intr_mask);
3174 skge_read32(hw, B0_IMSK);
3175 spin_unlock_irqrestore(&hw->hw_lock, flags);
3184 static void skge_mac_parity(struct skge_hw *hw, int port)
3186 struct net_device *dev = hw->dev[port];
3190 if (hw->chip_id == CHIP_ID_GENESIS)
3191 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3195 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3196 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3200 static void skge_mac_intr(struct skge_hw *hw, int port)
3202 if (hw->chip_id == CHIP_ID_GENESIS)
3203 genesis_mac_intr(hw, port);
3205 yukon_mac_intr(hw, port);
3209 static void skge_error_irq(struct skge_hw *hw)
3211 struct pci_dev *pdev = hw->pdev;
3212 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3214 if (hw->chip_id == CHIP_ID_GENESIS) {
3217 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3219 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3223 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3228 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3233 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3237 skge_mac_parity(hw, 0);
3240 skge_mac_parity(hw, 1);
3244 hw->dev[0]->name);
3245 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3250 hw->dev[1]->name);
3251 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3265 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3269 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3272 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3274 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3275 hw->intr_mask &= ~IS_HW_ERR;
3287 struct skge_hw *hw = (struct skge_hw *) arg;
3290 for (port = 0; port < hw->ports; port++) {
3291 struct net_device *dev = hw->dev[port];
3296 spin_lock(&hw->phy_lock);
3297 if (hw->chip_id != CHIP_ID_GENESIS)
3299 else if (hw->phy_type == SK_PHY_BCOM)
3301 spin_unlock(&hw->phy_lock);
3305 spin_lock_irq(&hw->hw_lock);
3306 hw->intr_mask |= IS_EXT_REG;
3307 skge_write32(hw, B0_IMSK, hw->intr_mask);
3308 skge_read32(hw, B0_IMSK);
3309 spin_unlock_irq(&hw->hw_lock);
3314 struct skge_hw *hw = dev_id;
3318 spin_lock(&hw->hw_lock);
3320 status = skge_read32(hw, B0_SP_ISRC);
3325 status &= hw->intr_mask;
3327 hw->intr_mask &= ~IS_EXT_REG;
3328 tasklet_schedule(&hw->phy_task);
3332 struct skge_port *skge = netdev_priv(hw->dev[0]);
3333 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3338 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3341 ++hw->dev[0]->stats.rx_over_errors;
3342 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3347 skge_mac_intr(hw, 0);
3349 if (hw->dev[1]) {
3350 struct skge_port *skge = netdev_priv(hw->dev[1]);
3353 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3358 ++hw->dev[1]->stats.rx_over_errors;
3359 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3363 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3366 skge_mac_intr(hw, 1);
3370 skge_error_irq(hw);
3372 skge_write32(hw, B0_IMSK, hw->intr_mask);
3373 skge_read32(hw, B0_IMSK);
3375 spin_unlock(&hw->hw_lock);
3386 skge_intr(dev->irq, skge->hw);
3394 struct skge_hw *hw = skge->hw;
3405 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3406 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3409 spin_lock_bh(&hw->phy_lock);
3410 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3411 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3413 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3414 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3416 if (hw->chip_id == CHIP_ID_GENESIS)
3417 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3419 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3420 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3423 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3424 spin_unlock_bh(&hw->phy_lock);
3440 static const char *skge_board_name(const struct skge_hw *hw)
3446 if (skge_chips[i].id == hw->chip_id)
3449 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3458 static int skge_reset(struct skge_hw *hw)
3465 ctst = skge_read16(hw, B0_CTST);
3468 skge_write8(hw, B0_CTST, CS_RST_SET);
3469 skge_write8(hw, B0_CTST, CS_RST_CLR);
3472 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3473 skge_write8(hw, B2_TST_CTRL2, 0);
3475 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3476 pci_write_config_word(hw->pdev, PCI_STATUS,
3478 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3479 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3482 skge_write16(hw, B0_CTST,
3485 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3486 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3487 pmd_type = skge_read8(hw, B2_PMD_TYP);
3488 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3490 switch (hw->chip_id) {
3492 switch (hw->phy_type) {
3494 hw->phy_addr = PHY_ADDR_XMAC;
3497 hw->phy_addr = PHY_ADDR_BCOM;
3500 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3501 hw->phy_type);
3509 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3510 hw->copper = 1;
3512 hw->phy_addr = PHY_ADDR_MARV;
3516 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3517 hw->chip_id);
3521 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3522 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3523 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3526 t8 = skge_read8(hw, B2_E_0);
3527 if (hw->chip_id == CHIP_ID_GENESIS) {
3530 hw->ram_size = 0x100000;
3531 hw->ram_offset = 0x80000;
3533 hw->ram_size = t8 * 512;
3535 hw->ram_size = 0x20000;
3537 hw->ram_size = t8 * 4096;
3539 hw->intr_mask = IS_HW_ERR;
3542 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3543 hw->intr_mask |= IS_EXT_REG;
3545 if (hw->chip_id == CHIP_ID_GENESIS)
3546 genesis_init(hw);
3549 skge_write8(hw, B0_POWER_CTRL,
3553 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3554 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3555 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3556 hw->intr_mask &= ~IS_HW_ERR;
3560 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3561 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3563 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3564 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3567 for (i = 0; i < hw->ports; i++) {
3568 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3569 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3574 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3575 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3576 skge_write8(hw, B0_LED, LED_STAT_ON);
3579 for (i = 0; i < hw->ports; i++)
3580 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3583 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3585 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3586 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3587 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3588 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3589 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3590 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3591 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3592 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3593 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3594 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3595 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3596 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3598 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3603 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3604 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3605 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3607 skge_write32(hw, B0_IMSK, hw->intr_mask);
3609 for (i = 0; i < hw->ports; i++) {
3610 if (hw->chip_id == CHIP_ID_GENESIS)
3611 genesis_reset(hw, i);
3613 yukon_reset(hw, i);
3628 const struct skge_hw *hw = skge->hw;
3634 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3635 skge_read32(hw, B0_IMSK));
3775 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3782 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3786 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3790 dev->irq = hw->pdev->irq;
3798 skge->hw = hw;
3809 skge->advertising = skge_supported_modes(hw);
3811 if (device_can_wakeup(&hw->pdev->dev)) {
3812 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3813 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3816 hw->dev[port] = dev;
3823 if (hw->chip_id != CHIP_ID_GENESIS) {
3829 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3852 struct skge_hw *hw;
3895 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3897 if (!hw) {
3901 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3903 hw->pdev = pdev;
3904 spin_lock_init(&hw->hw_lock);
3905 spin_lock_init(&hw->phy_lock);
3906 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
3908 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3909 if (!hw->regs) {
3914 err = skge_reset(hw);
3921 skge_board_name(hw), hw->chip_rev);
3923 dev = skge_devinit(hw, 0, using_dac);
3937 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
3945 if (hw->ports > 1) {
3946 dev1 = skge_devinit(hw, 1, using_dac);
3952 hw->dev[1] = NULL;
3953 hw->ports = 1;
3958 pci_set_drvdata(pdev, hw);
3967 skge_write16(hw, B0_LED, LED_STAT_OFF);
3969 iounmap(hw->regs);
3971 kfree(hw);
3983 struct skge_hw *hw = pci_get_drvdata(pdev);
3986 if (!hw)
3991 dev1 = hw->dev[1];
3994 dev0 = hw->dev[0];
3997 tasklet_disable(&hw->phy_task);
3999 spin_lock_irq(&hw->hw_lock);
4000 hw->intr_mask = 0;
4001 skge_write32(hw, B0_IMSK, 0);
4002 skge_read32(hw, B0_IMSK);
4003 spin_unlock_irq(&hw->hw_lock);
4005 skge_write16(hw, B0_LED, LED_STAT_OFF);
4006 skge_write8(hw, B0_CTST, CS_RST_SET);
4008 free_irq(pdev->irq, hw);
4015 iounmap(hw->regs);
4016 kfree(hw);
4023 struct skge_hw *hw = pci_get_drvdata(pdev);
4026 if (!hw)
4033 for (i = 0; i < hw->ports; i++) {
4034 struct net_device *dev = hw->dev[i];
4045 skge_write32(hw, B0_IMSK, 0);
4054 struct skge_hw *hw = pci_get_drvdata(pdev);
4057 if (!hw)
4068 err = skge_reset(hw);
4072 for (i = 0; i < hw->ports; i++) {
4073 struct net_device *dev = hw->dev[i];
4092 struct skge_hw *hw = pci_get_drvdata(pdev);
4095 if (!hw)
4098 for (i = 0; i < hw->ports; i++) {
4099 struct net_device *dev = hw->dev[i];