Lines Matching refs:ctrl_outl
48 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
50 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
60 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR);
63 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR);
99 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
101 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
111 ctrl_outl(0, ioaddr + RTRATE);
114 ctrl_outl(1, ioaddr + RTRATE);
146 ctrl_outl(ARSTR_ARSTR, ARSTR);
155 ctrl_outl(EDSR_ENALL, ioaddr + EDSR);
156 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
167 ctrl_outl(0x0, ioaddr + TDLAR);
168 ctrl_outl(0x0, ioaddr + TDFAR);
169 ctrl_outl(0x0, ioaddr + TDFXR);
170 ctrl_outl(0x0, ioaddr + TDFFR);
171 ctrl_outl(0x0, ioaddr + RDLAR);
172 ctrl_outl(0x0, ioaddr + RDFAR);
173 ctrl_outl(0x0, ioaddr + RDFXR);
174 ctrl_outl(0x0, ioaddr + RDFFR);
183 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
185 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
195 ctrl_outl(GECMR_10, ioaddr + GECMR);
198 ctrl_outl(GECMR_100, ioaddr + GECMR);
201 ctrl_outl(GECMR_1000, ioaddr + GECMR);
286 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
288 ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
339 ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
342 ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]),
382 ctrl_outl(ctrl_inl(addr) | msk, addr);
388 ctrl_outl((ctrl_inl(addr) & ~msk), addr);
509 ctrl_outl(mdp->rx_desc_dma, ioaddr + RDLAR);
511 ctrl_outl(mdp->rx_desc_dma, ioaddr + RDFAR);
531 ctrl_outl(mdp->tx_desc_dma, ioaddr + TDLAR);
533 ctrl_outl(mdp->tx_desc_dma, ioaddr + TDFAR);
626 ctrl_outl(mdp->cd->rpadir_value, ioaddr + RPADIR);
629 ctrl_outl(0, ioaddr + EESIPR);
633 ctrl_outl(EDMR_EL, ioaddr + EDMR);
636 ctrl_outl(0, ioaddr + EDMR);
639 ctrl_outl(mdp->cd->fdr_value, ioaddr + FDR);
640 ctrl_outl(0, ioaddr + TFTR);
643 ctrl_outl(mdp->cd->rmcr_value, ioaddr + RMCR);
647 ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);
650 ctrl_outl(0x800, ioaddr + BCULR); /* Burst sycle set */
652 ctrl_outl(mdp->cd->fcftr_value, ioaddr + FCFTR);
655 ctrl_outl(0, ioaddr + TRIMD);
658 ctrl_outl(RFLR_VALUE, ioaddr + RFLR);
660 ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
661 ctrl_outl(mdp->cd->eesipr_value, ioaddr + EESIPR);
667 ctrl_outl(val, ioaddr + ECMR);
673 ctrl_outl(mdp->cd->ecsr_value, ioaddr + ECSR);
676 ctrl_outl(mdp->cd->ecsipr_value, ioaddr + ECSIPR);
683 ctrl_outl(APR_AP, ioaddr + APR);
685 ctrl_outl(MPR_MP, ioaddr + MPR);
687 ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
690 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
815 ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR);
831 ctrl_outl(felic_stat, ioaddr + ECSR); /* clear int */
848 ctrl_outl(ctrl_inl(ioaddr + ECMR) &
852 ctrl_outl(ctrl_inl(ioaddr + EESIPR) &
855 ctrl_outl(ctrl_inl(ioaddr + ECSR),
857 ctrl_outl(ctrl_inl(ioaddr + EESIPR) |
860 ctrl_outl(ctrl_inl(ioaddr + ECMR) |
892 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
918 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
942 ctrl_outl(intr_status, ioaddr + EESR);
1003 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF)
1199 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
1214 ctrl_outl(0x0000, ioaddr + EESIPR);
1217 ctrl_outl(0, ioaddr + EDTRR);
1218 ctrl_outl(0, ioaddr + EDRRR);
1254 ctrl_outl(0, ioaddr + TROCR); /* (write clear) */
1256 ctrl_outl(0, ioaddr + CDCR); /* (write clear) */
1258 ctrl_outl(0, ioaddr + LCCR); /* (write clear) */
1261 ctrl_outl(0, ioaddr + CERCR); /* (write clear) */
1263 ctrl_outl(0, ioaddr + CEECR); /* (write clear) */
1266 ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */
1297 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM,
1301 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT,
1309 ctrl_outl(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */
1310 ctrl_outl(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */
1311 ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */
1312 ctrl_outl(0xc, ioaddr + TSU_BSYSL0);
1313 ctrl_outl(0xc, ioaddr + TSU_BSYSL1);
1314 ctrl_outl(0, ioaddr + TSU_PRISL0);
1315 ctrl_outl(0, ioaddr + TSU_PRISL1);
1316 ctrl_outl(0, ioaddr + TSU_FWSL0);
1317 ctrl_outl(0, ioaddr + TSU_FWSL1);
1318 ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
1320 ctrl_outl(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */
1321 ctrl_outl(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */
1323 ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */
1324 ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */
1326 ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */
1327 ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */
1328 ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */
1329 ctrl_outl(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */
1330 ctrl_outl(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */
1331 ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */
1332 ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */