Lines Matching refs:bar0
1080 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1084 val64 = readq(&bar0->pci_mode);
1114 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1120 val64 = readq(&bar0->pci_mode);
1182 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1206 writeq(val64, &bar0->tti_data1_mem);
1231 writeq(val64, &bar0->tti_data2_mem);
1236 writeq(val64, &bar0->tti_command_mem);
1238 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1258 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1281 writeq(val64, &bar0->sw_reset);
1283 val64 = readq(&bar0->sw_reset);
1288 writeq(val64, &bar0->sw_reset);
1290 val64 = readq(&bar0->sw_reset);
1297 val64 = readq(&bar0->adapter_status);
1307 add = &bar0->mac_cfg;
1308 val64 = readq(&bar0->mac_cfg);
1310 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1312 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1316 val64 = readq(&bar0->mac_int_mask);
1317 val64 = readq(&bar0->mc_int_mask);
1318 val64 = readq(&bar0->xgxs_int_mask);
1322 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1327 &bar0->dtx_control, UF);
1335 &bar0->dtx_control, UF);
1336 val64 = readq(&bar0->dtx_control);
1343 writeq(val64, &bar0->tx_fifo_partition_0);
1344 writeq(val64, &bar0->tx_fifo_partition_1);
1345 writeq(val64, &bar0->tx_fifo_partition_2);
1346 writeq(val64, &bar0->tx_fifo_partition_3);
1361 writeq(val64, &bar0->tx_fifo_partition_0);
1366 writeq(val64, &bar0->tx_fifo_partition_1);
1371 writeq(val64, &bar0->tx_fifo_partition_2);
1376 writeq(val64, &bar0->tx_fifo_partition_3);
1391 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1393 val64 = readq(&bar0->tx_fifo_partition_0);
1395 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1401 val64 = readq(&bar0->tx_pa_cfg);
1406 writeq(val64, &bar0->tx_pa_cfg);
1415 writeq(val64, &bar0->rx_queue_priority);
1464 writeq(val64, &bar0->rx_queue_cfg);
1473 writeq(val64, &bar0->tx_w_round_robin_0);
1474 writeq(val64, &bar0->tx_w_round_robin_1);
1475 writeq(val64, &bar0->tx_w_round_robin_2);
1476 writeq(val64, &bar0->tx_w_round_robin_3);
1477 writeq(val64, &bar0->tx_w_round_robin_4);
1481 writeq(val64, &bar0->tx_w_round_robin_0);
1482 writeq(val64, &bar0->tx_w_round_robin_1);
1483 writeq(val64, &bar0->tx_w_round_robin_2);
1484 writeq(val64, &bar0->tx_w_round_robin_3);
1486 writeq(val64, &bar0->tx_w_round_robin_4);
1490 writeq(val64, &bar0->tx_w_round_robin_0);
1492 writeq(val64, &bar0->tx_w_round_robin_1);
1494 writeq(val64, &bar0->tx_w_round_robin_2);
1496 writeq(val64, &bar0->tx_w_round_robin_3);
1498 writeq(val64, &bar0->tx_w_round_robin_4);
1502 writeq(val64, &bar0->tx_w_round_robin_0);
1503 writeq(val64, &bar0->tx_w_round_robin_1);
1504 writeq(val64, &bar0->tx_w_round_robin_2);
1505 writeq(val64, &bar0->tx_w_round_robin_3);
1507 writeq(val64, &bar0->tx_w_round_robin_4);
1511 writeq(val64, &bar0->tx_w_round_robin_0);
1513 writeq(val64, &bar0->tx_w_round_robin_1);
1515 writeq(val64, &bar0->tx_w_round_robin_2);
1517 writeq(val64, &bar0->tx_w_round_robin_3);
1519 writeq(val64, &bar0->tx_w_round_robin_4);
1523 writeq(val64, &bar0->tx_w_round_robin_0);
1525 writeq(val64, &bar0->tx_w_round_robin_1);
1527 writeq(val64, &bar0->tx_w_round_robin_2);
1529 writeq(val64, &bar0->tx_w_round_robin_3);
1531 writeq(val64, &bar0->tx_w_round_robin_4);
1535 writeq(val64, &bar0->tx_w_round_robin_0);
1537 writeq(val64, &bar0->tx_w_round_robin_1);
1539 writeq(val64, &bar0->tx_w_round_robin_2);
1541 writeq(val64, &bar0->tx_w_round_robin_3);
1543 writeq(val64, &bar0->tx_w_round_robin_4);
1547 writeq(val64, &bar0->tx_w_round_robin_0);
1548 writeq(val64, &bar0->tx_w_round_robin_1);
1549 writeq(val64, &bar0->tx_w_round_robin_2);
1550 writeq(val64, &bar0->tx_w_round_robin_3);
1552 writeq(val64, &bar0->tx_w_round_robin_4);
1557 val64 = readq(&bar0->tx_fifo_partition_0);
1559 writeq(val64, &bar0->tx_fifo_partition_0);
1568 writeq(val64, &bar0->rx_w_round_robin_0);
1569 writeq(val64, &bar0->rx_w_round_robin_1);
1570 writeq(val64, &bar0->rx_w_round_robin_2);
1571 writeq(val64, &bar0->rx_w_round_robin_3);
1572 writeq(val64, &bar0->rx_w_round_robin_4);
1575 writeq(val64, &bar0->rts_qos_steering);
1579 writeq(val64, &bar0->rx_w_round_robin_0);
1580 writeq(val64, &bar0->rx_w_round_robin_1);
1581 writeq(val64, &bar0->rx_w_round_robin_2);
1582 writeq(val64, &bar0->rx_w_round_robin_3);
1584 writeq(val64, &bar0->rx_w_round_robin_4);
1587 writeq(val64, &bar0->rts_qos_steering);
1591 writeq(val64, &bar0->rx_w_round_robin_0);
1593 writeq(val64, &bar0->rx_w_round_robin_1);
1595 writeq(val64, &bar0->rx_w_round_robin_2);
1597 writeq(val64, &bar0->rx_w_round_robin_3);
1599 writeq(val64, &bar0->rx_w_round_robin_4);
1602 writeq(val64, &bar0->rts_qos_steering);
1606 writeq(val64, &bar0->rx_w_round_robin_0);
1607 writeq(val64, &bar0->rx_w_round_robin_1);
1608 writeq(val64, &bar0->rx_w_round_robin_2);
1609 writeq(val64, &bar0->rx_w_round_robin_3);
1611 writeq(val64, &bar0->rx_w_round_robin_4);
1614 writeq(val64, &bar0->rts_qos_steering);
1618 writeq(val64, &bar0->rx_w_round_robin_0);
1620 writeq(val64, &bar0->rx_w_round_robin_1);
1622 writeq(val64, &bar0->rx_w_round_robin_2);
1624 writeq(val64, &bar0->rx_w_round_robin_3);
1626 writeq(val64, &bar0->rx_w_round_robin_4);
1629 writeq(val64, &bar0->rts_qos_steering);
1633 writeq(val64, &bar0->rx_w_round_robin_0);
1635 writeq(val64, &bar0->rx_w_round_robin_1);
1637 writeq(val64, &bar0->rx_w_round_robin_2);
1639 writeq(val64, &bar0->rx_w_round_robin_3);
1641 writeq(val64, &bar0->rx_w_round_robin_4);
1644 writeq(val64, &bar0->rts_qos_steering);
1648 writeq(val64, &bar0->rx_w_round_robin_0);
1650 writeq(val64, &bar0->rx_w_round_robin_1);
1652 writeq(val64, &bar0->rx_w_round_robin_2);
1654 writeq(val64, &bar0->rx_w_round_robin_3);
1656 writeq(val64, &bar0->rx_w_round_robin_4);
1659 writeq(val64, &bar0->rts_qos_steering);
1663 writeq(val64, &bar0->rx_w_round_robin_0);
1664 writeq(val64, &bar0->rx_w_round_robin_1);
1665 writeq(val64, &bar0->rx_w_round_robin_2);
1666 writeq(val64, &bar0->rx_w_round_robin_3);
1668 writeq(val64, &bar0->rx_w_round_robin_4);
1671 writeq(val64, &bar0->rts_qos_steering);
1678 writeq(val64, &bar0->rts_frm_len_n[i]);
1683 writeq(val64, &bar0->rts_frm_len_n[i]);
1697 &bar0->rts_frm_len_n[i]);
1712 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1716 writeq(val64, &bar0->stat_byte_cnt);
1725 writeq(val64, &bar0->mac_link_util);
1751 writeq(val64, &bar0->rti_data1_mem);
1761 writeq(val64, &bar0->rti_data2_mem);
1767 writeq(val64, &bar0->rti_command_mem);
1778 val64 = readq(&bar0->rti_command_mem);
1796 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1797 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1800 add = &bar0->mac_cfg;
1801 val64 = readq(&bar0->mac_cfg);
1803 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1805 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1807 val64 = readq(&bar0->mac_cfg);
1810 add = &bar0->mac_cfg;
1811 val64 = readq(&bar0->mac_cfg);
1814 writeq(val64, &bar0->mac_cfg);
1816 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1818 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1826 val64 = readq(&bar0->rmac_pause_cfg);
1829 writeq(val64, &bar0->rmac_pause_cfg);
1843 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1851 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1857 val64 = readq(&bar0->pic_control);
1859 writeq(val64, &bar0->pic_control);
1862 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1863 writeq(0x0, &bar0->read_retry_delay);
1864 writeq(0x0, &bar0->write_retry_delay);
1874 writeq(val64, &bar0->misc_control);
1875 val64 = readq(&bar0->pic_control2);
1877 writeq(val64, &bar0->pic_control2);
1881 writeq(val64, &bar0->tmac_avg_ipg);
1921 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1925 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1932 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1937 &bar0->pfc_err_mask);
1941 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1949 flag, &bar0->pcc_err_mask);
1952 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1957 flag, &bar0->lso_err_mask);
1960 flag, &bar0->tpa_err_mask);
1962 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1968 &bar0->mac_int_mask);
1972 flag, &bar0->mac_tmac_err_mask);
1978 &bar0->xgxs_int_mask);
1981 flag, &bar0->xgxs_txgxs_err_mask);
1988 flag, &bar0->rxdma_int_mask);
1992 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1996 &bar0->prc_pcix_err_mask);
1999 &bar0->rpa_err_mask);
2005 flag, &bar0->rda_err_mask);
2008 flag, &bar0->rti_err_mask);
2014 &bar0->mac_int_mask);
2021 flag, &bar0->mac_rmac_err_mask);
2027 &bar0->xgxs_int_mask);
2029 &bar0->xgxs_rxgxs_err_mask);
2035 flag, &bar0->mc_int_mask);
2038 &bar0->mc_err_mask);
2059 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2079 &bar0->pic_int_mask);
2081 &bar0->gpio_int_mask);
2083 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2089 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2101 writeq(0x0, &bar0->tx_traffic_mask);
2107 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2116 writeq(0x0, &bar0->rx_traffic_mask);
2122 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2126 temp64 = readq(&bar0->general_int_mask);
2131 writeq(temp64, &bar0->general_int_mask);
2133 nic->general_int_mask = readq(&bar0->general_int_mask);
2144 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2145 u64 val64 = readq(&bar0->adapter_status);
2184 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2185 u64 val64 = readq(&bar0->adapter_status);
2250 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2255 writeq(fix_mac[i++], &bar0->gpio_control);
2257 val64 = readq(&bar0->gpio_control);
2276 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2288 &bar0->prc_rxd0_n[i]);
2290 val64 = readq(&bar0->prc_ctrl_n[i]);
2299 writeq(val64, &bar0->prc_ctrl_n[i]);
2304 val64 = readq(&bar0->rx_pa_cfg);
2306 writeq(val64, &bar0->rx_pa_cfg);
2310 val64 = readq(&bar0->rx_pa_cfg);
2312 writeq(val64, &bar0->rx_pa_cfg);
2321 val64 = readq(&bar0->mc_rldram_mrs);
2323 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2324 val64 = readq(&bar0->mc_rldram_mrs);
2329 val64 = readq(&bar0->adapter_control);
2331 writeq(val64, &bar0->adapter_control);
2337 val64 = readq(&bar0->adapter_status);
2354 val64 = readq(&bar0->adapter_control);
2356 writeq(val64, &bar0->adapter_control);
2369 val64 = readq(&bar0->gpio_control);
2371 writeq(val64, &bar0->gpio_control);
2373 writeq(val64, (void __iomem *)bar0 + 0x2700);
2475 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2486 val64 = readq(&bar0->adapter_control);
2488 writeq(val64, &bar0->adapter_control);
2841 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2853 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2867 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2887 writeq(0, &bar0->rx_traffic_mask);
2888 readl(&bar0->rx_traffic_mask);
2906 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2917 writeq(val64, &bar0->rx_traffic_int);
2918 writeq(val64, &bar0->tx_traffic_int);
3163 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3169 writeq(val64, &bar0->mdio_control);
3171 writeq(val64, &bar0->mdio_control);
3180 writeq(val64, &bar0->mdio_control);
3182 writeq(val64, &bar0->mdio_control);
3189 writeq(val64, &bar0->mdio_control);
3191 writeq(val64, &bar0->mdio_control);
3209 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3215 writeq(val64, &bar0->mdio_control);
3217 writeq(val64, &bar0->mdio_control);
3225 writeq(val64, &bar0->mdio_control);
3227 writeq(val64, &bar0->mdio_control);
3231 rval64 = readq(&bar0->mdio_control);
3470 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3487 writeq(val64, &bar0->sw_reset);
3527 writeq(s2BIT(62), &bar0->txpic_int_reg);
3562 val64 = readq(&bar0->gpio_control);
3564 writeq(val64, &bar0->gpio_control);
3566 writeq(val64, (void __iomem *)bar0 + 0x2700);
3574 val64 = readq(&bar0->pcc_err_reg);
3575 writeq(val64, &bar0->pcc_err_reg);
3594 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3602 val64 = readq(&bar0->pif_rd_swapper_fb);
3611 writeq(value[i], &bar0->swapper_ctrl);
3612 val64 = readq(&bar0->pif_rd_swapper_fb);
3625 valr = readq(&bar0->swapper_ctrl);
3629 writeq(valt, &bar0->xmsi_address);
3630 val64 = readq(&bar0->xmsi_address);
3640 writeq((value[i] | valr), &bar0->swapper_ctrl);
3641 writeq(valt, &bar0->xmsi_address);
3642 val64 = readq(&bar0->xmsi_address);
3654 val64 = readq(&bar0->swapper_ctrl);
3675 writeq(val64, &bar0->swapper_ctrl);
3699 writeq(val64, &bar0->swapper_ctrl);
3701 val64 = readq(&bar0->swapper_ctrl);
3707 val64 = readq(&bar0->pif_rd_swapper_fb);
3721 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3726 val64 = readq(&bar0->xmsi_access);
3742 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3751 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3752 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3754 writeq(val64, &bar0->xmsi_access);
3765 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3776 writeq(val64, &bar0->xmsi_access);
3782 addr = readq(&bar0->xmsi_address);
3783 data = readq(&bar0->xmsi_data);
3793 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3837 rx_mat = readq(&bar0->rx_mat);
3845 writeq(rx_mat, &bar0->rx_mat);
3846 readq(&bar0->rx_mat);
3889 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3904 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3908 writeq(val64, &bar0->scheduled_int_ctrl);
3923 writeq(saved64, &bar0->scheduled_int_ctrl);
4317 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4326 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4345 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4352 reason = readq(&bar0->general_int_status);
4358 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4364 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4369 writeq(sp->general_int_mask, &bar0->general_int_mask);
4370 readl(&bar0->general_int_status);
4379 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4382 val64 = readq(&bar0->pic_int_status);
4384 val64 = readq(&bar0->gpio_int_reg);
4393 writeq(val64, &bar0->gpio_int_reg);
4394 val64 = readq(&bar0->gpio_int_mask);
4397 writeq(val64, &bar0->gpio_int_mask);
4399 val64 = readq(&bar0->adapter_status);
4401 val64 = readq(&bar0->adapter_control);
4403 writeq(val64, &bar0->adapter_control);
4405 writeq(val64, &bar0->adapter_control);
4414 val64 = readq(&bar0->gpio_int_mask);
4417 writeq(val64, &bar0->gpio_int_mask);
4420 val64 = readq(&bar0->adapter_status);
4423 val64 = readq(&bar0->gpio_int_mask);
4426 writeq(val64, &bar0->gpio_int_mask);
4429 val64 = readq(&bar0->adapter_control);
4431 writeq(val64, &bar0->adapter_control);
4434 val64 = readq(&bar0->gpio_int_mask);
4473 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4501 val64 = readq(&bar0->mac_rmac_err_reg);
4502 writeq(val64, &bar0->mac_rmac_err_reg);
4508 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4513 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4519 val64 = readq(&bar0->ring_bump_counter1);
4526 val64 = readq(&bar0->ring_bump_counter2);
4534 val64 = readq(&bar0->txdma_int_status);
4540 &bar0->pfc_err_reg,
4544 &bar0->pfc_err_reg,
4553 &bar0->tda_err_reg,
4557 &bar0->tda_err_reg,
4567 &bar0->pcc_err_reg,
4571 &bar0->pcc_err_reg,
4578 &bar0->tti_err_reg,
4582 &bar0->tti_err_reg,
4590 &bar0->lso_err_reg,
4594 &bar0->lso_err_reg,
4601 &bar0->tpa_err_reg,
4605 &bar0->tpa_err_reg,
4612 &bar0->sm_err_reg,
4617 val64 = readq(&bar0->mac_int_status);
4620 &bar0->mac_tmac_err_reg,
4626 &bar0->mac_tmac_err_reg,
4630 val64 = readq(&bar0->xgxs_int_status);
4633 &bar0->xgxs_txgxs_err_reg,
4637 &bar0->xgxs_txgxs_err_reg,
4641 val64 = readq(&bar0->rxdma_int_status);
4647 &bar0->rc_err_reg,
4652 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4657 &bar0->prc_pcix_err_reg,
4663 &bar0->prc_pcix_err_reg,
4669 &bar0->rpa_err_reg,
4673 &bar0->rpa_err_reg,
4683 &bar0->rda_err_reg,
4690 &bar0->rda_err_reg,
4696 &bar0->rti_err_reg,
4700 &bar0->rti_err_reg,
4704 val64 = readq(&bar0->mac_int_status);
4707 &bar0->mac_rmac_err_reg,
4713 &bar0->mac_rmac_err_reg,
4717 val64 = readq(&bar0->xgxs_int_status);
4720 &bar0->xgxs_rxgxs_err_reg,
4725 val64 = readq(&bar0->mc_int_status);
4728 &bar0->mc_err_reg,
4734 writeq(val64, &bar0->mc_err_reg);
4775 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4798 reason = readq(&bar0->general_int_status);
4805 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4810 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4811 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4812 readl(&bar0->rx_traffic_int);
4821 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4836 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4854 writeq(sp->general_int_mask, &bar0->general_int_mask);
4855 readl(&bar0->general_int_status);
4872 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4880 writeq(val64, &bar0->stat_cfg);
4883 val64 = readq(&bar0->stat_cfg);
4999 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5009 &bar0->rmac_addr_data0_mem);
5011 &bar0->rmac_addr_data1_mem);
5015 writeq(val64, &bar0->rmac_addr_cmd_mem);
5017 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5026 &bar0->rmac_addr_data0_mem);
5028 &bar0->rmac_addr_data1_mem);
5032 writeq(val64, &bar0->rmac_addr_cmd_mem);
5034 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5044 add = &bar0->mac_cfg;
5045 val64 = readq(&bar0->mac_cfg);
5048 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5050 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5054 val64 = readq(&bar0->rx_pa_cfg);
5056 writeq(val64, &bar0->rx_pa_cfg);
5060 val64 = readq(&bar0->mac_cfg);
5066 add = &bar0->mac_cfg;
5067 val64 = readq(&bar0->mac_cfg);
5070 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5072 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5076 val64 = readq(&bar0->rx_pa_cfg);
5078 writeq(val64, &bar0->rx_pa_cfg);
5082 val64 = readq(&bar0->mac_cfg);
5104 &bar0->rmac_addr_data0_mem);
5106 &bar0->rmac_addr_data1_mem);
5111 writeq(val64, &bar0->rmac_addr_cmd_mem);
5114 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5136 &bar0->rmac_addr_data0_mem);
5138 &bar0->rmac_addr_data1_mem);
5143 writeq(val64, &bar0->rmac_addr_cmd_mem);
5146 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5233 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5236 &bar0->rmac_addr_data0_mem);
5240 writeq(val64, &bar0->rmac_addr_cmd_mem);
5243 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5279 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5284 writeq(val64, &bar0->rmac_addr_cmd_mem);
5287 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5293 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5484 reg = readq(sp->bar0 + i);
5501 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5508 val64 = readq(&bar0->gpio_control);
5510 writeq(val64, &bar0->gpio_control);
5512 val64 = readq(&bar0->adapter_control);
5514 writeq(val64, &bar0->adapter_control);
5539 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5543 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5545 val64 = readq(&bar0->adapter_control);
5564 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5565 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5618 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5620 val64 = readq(&bar0->rmac_pause_cfg);
5645 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5647 val64 = readq(&bar0->rmac_pause_cfg);
5656 writeq(val64, &bar0->rmac_pause_cfg);
5682 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5690 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5693 val64 = readq(&bar0->i2c_control);
5708 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5710 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5712 val64 = readq(&bar0->spi_control);
5717 *data = readq(&bar0->spi_data);
5748 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5756 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5759 val64 = readq(&bar0->i2c_control);
5772 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5777 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5779 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5781 val64 = readq(&bar0->spi_control);
5968 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5972 val64 = readq(&bar0->pif_rd_swapper_fb);
5978 val64 = readq(&bar0->rmac_pause_cfg);
5984 val64 = readq(&bar0->rx_queue_cfg);
5994 val64 = readq(&bar0->xgxs_efifo_cfg);
6001 writeq(val64, &bar0->xmsi_data);
6002 val64 = readq(&bar0->xmsi_data);
6009 writeq(val64, &bar0->xmsi_data);
6010 val64 = readq(&bar0->xmsi_data);
6173 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6176 val64 = readq(&bar0->adapter_status);
6200 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6204 val64 = readq(&bar0->adapter_control);
6206 writeq(val64, &bar0->adapter_control);
6208 val64 = readq(&bar0->mc_rldram_test_ctrl);
6210 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6212 val64 = readq(&bar0->mc_rldram_mrs);
6214 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6217 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6223 writeq(val64, &bar0->mc_rldram_test_d0);
6228 writeq(val64, &bar0->mc_rldram_test_d1);
6233 writeq(val64, &bar0->mc_rldram_test_d2);
6236 writeq(val64, &bar0->mc_rldram_test_add);
6241 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6244 val64 = readq(&bar0->mc_rldram_test_ctrl);
6254 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6257 val64 = readq(&bar0->mc_rldram_test_ctrl);
6266 val64 = readq(&bar0->mc_rldram_test_ctrl);
6276 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6843 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6846 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6863 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6886 val64 = readq(&bar0->adapter_status);
6888 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6890 val64 = readq(&bar0->adapter_control);
6892 writeq(val64, &bar0->adapter_control);
6895 val64 = readq(&bar0->gpio_control);
6897 writeq(val64, &bar0->gpio_control);
6898 val64 = readq(&bar0->gpio_control);
6901 writeq(val64, &bar0->adapter_control);
6911 val64 = readq(&bar0->adapter_control);
6913 writeq(val64, &bar0->adapter_control);
6918 val64 = readq(&bar0->gpio_control);
6920 writeq(val64, &bar0->gpio_control);
6921 val64 = readq(&bar0->gpio_control);
6924 val64 = readq(&bar0->adapter_control);
6926 writeq(val64, &bar0->adapter_control);
7204 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7249 val64 = readq(&bar0->adapter_status);
7777 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7784 writeq(val64, &bar0->rts_ds_mem_data);
7790 writeq(val64, &bar0->rts_ds_mem_ctrl);
7792 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7838 struct XENA_dev_config __iomem *bar0 = NULL;
8020 sp->bar0 = pci_ioremap_bar(pdev, 0);
8021 if (!sp->bar0) {
8037 dev->base_addr = (unsigned long)sp->bar0;
8127 bar0 = sp->bar0;
8130 writeq(val64, &bar0->rmac_addr_cmd_mem);
8131 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8134 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8193 val64 = readq(&bar0->gpio_control);
8195 writeq(val64, &bar0->gpio_control);
8197 writeq(val64, (void __iomem *)bar0 + 0x2700);
8198 val64 = readq(&bar0->gpio_control);
8314 iounmap(sp->bar0);
8352 iounmap(sp->bar0);