Lines Matching refs:vBIT
46 #define SW_RESET_XENA vBIT(0xA5,0,8)
47 #define SW_RESET_FLASH vBIT(0xA5,8,8)
48 #define SW_RESET_EOI vBIT(0xA5,16,8)
64 #define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
65 #define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8)
66 #define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
77 #define ADAPTER_UDPI(val) vBIT(val,36,4)
96 #define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60)
192 #define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5)
224 #define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6)
228 #define TXREQTO_VAL(val) vBIT(val,0,32)
246 #define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8)
251 #define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8)
255 #define STAT_BC(n) vBIT(n,4,12)
265 #define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
266 #define SET_UPDT_CLICKS(val) vBIT(val, 32, 32)
272 #define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16)
273 #define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5)
274 #define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5)
275 #define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4)
276 #define MDIO_OP(val) vBIT(val, 60, 2)
281 #define MDIO_MDIO_DATA(val) vBIT(val, 32, 16)
286 #define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
287 #define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
288 #define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
291 #define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
292 #define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
294 #define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
301 #define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
309 #define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
334 #define TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8)
335 #define TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8)
343 #define PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8)
344 #define PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8)
345 #define PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8)
346 #define PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8)
347 #define PCC_SM_ERR_ALARM vBIT(0xff,32,8)
348 #define PCC_WR_ERR_ALARM vBIT(0xff,40,8)
349 #define PCC_N_SERR vBIT(0xff,48,8)
354 #define PCC_ENABLE_FOUR vBIT(0x0F,0,8)
397 #define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
398 #define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
399 #define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
400 #define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
403 #define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
404 #define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
405 #define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
406 #define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
409 #define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
410 #define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
411 #define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
412 #define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
415 #define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
416 #define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
417 #define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
418 #define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
439 #define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
442 #define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
443 #define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
446 #define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
447 #define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
448 #define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
451 #define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
452 #define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
453 #define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
454 #define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
482 #define RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8)
483 #define RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8)
495 #define RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8)
496 #define RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8)
499 #define RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8)
501 #define RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8)
506 #define PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8)
507 #define PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8)
508 #define PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8)
509 #define PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8)
510 #define PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8)
511 #define PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8)
535 #define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
536 #define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
537 #define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
538 #define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
539 #define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
540 #define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
541 #define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
542 #define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
565 #define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
566 #define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
567 #define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
568 #define PRC_CTRL_RING_MODE_x vBIT(3,14,2)
574 #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
600 #define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
603 #define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
606 #define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
607 #define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
608 #define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
611 #define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
612 #define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
613 #define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
614 #define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
694 #define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
697 #define TMAC_AVG_IPG(val) vBIT(val,0,8)
700 #define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
701 #define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)
702 #define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14)
715 #define RMAC_CFG_KEY(val) vBIT(val,0,16)
733 #define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
736 #define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
740 #define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
748 #define RMAC_ADDR_BCAST_EN vBIT(0)_48
749 #define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
758 #define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
759 #define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
767 #define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
768 #define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
769 #define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
770 #define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
771 #define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
772 #define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
780 #define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
787 #define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
801 #define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
804 #define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
805 #define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
811 #define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
813 #define RTS_DS_MEM_DATA(n) vBIT(n,0,8)
848 #define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
849 #define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
850 #define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
851 #define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
852 #define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
853 #define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
854 #define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
855 #define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
893 #define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16)
939 #define SPI_CONTROL_KEY(key) vBIT(key,0,4)
940 #define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3)
941 #define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8)
942 #define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24)
948 #define SPI_DATA_WRITE(data,len) vBIT(data,0,len)