Lines Matching refs:RTL_W32
88 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
551 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
573 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
629 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
644 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
661 RTL_W32(CSIDR, value);
662 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
677 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
696 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
745 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
891 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
893 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1220 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1222 RTL_W32(CounterAddrLow, cmd);
1223 RTL_W32(CounterAddrLow, cmd | CounterDump);
1234 RTL_W32(CounterAddrLow, 0);
1235 RTL_W32(CounterAddrHigh, 0);
2858 RTL_W32(MAC4, high);
2861 RTL_W32(MAC0, low);
3368 RTL_W32(RxConfig, cfg);
3371 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3405 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3406 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3407 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3408 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3444 RTL_W32(0x7c, p->val);
3512 RTL_W32(RxMissed, 0);
3748 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4699 RTL_W32(RxMissed, 0);
4821 RTL_W32(MAR0 + 4, mc_filter[1]);
4822 RTL_W32(MAR0 + 0, mc_filter[0]);
4824 RTL_W32(RxConfig, tmp);