Lines Matching refs:RTL_R32
91 #define RTL_R32(reg) readl (ioaddr + (reg))
558 if (!(RTL_R32(PHYAR) & 0x80000000))
580 if (RTL_R32(PHYAR) & 0x80000000) {
581 value = RTL_R32(PHYAR) & 0xffff;
633 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
647 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
648 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
666 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
681 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
682 value = RTL_R32(CSIDR);
699 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
700 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
725 return RTL_R32(TBICSR) & TBIReset;
735 return RTL_R32(TBICSR) & TBILinkOk;
745 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
888 reg = RTL_R32(TBICSR);
1114 status = RTL_R32(TBICSR);
1226 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1303 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1307 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1366 reg = RTL_R32(TxConfig);
2859 RTL_R32(MAC4);
2862 RTL_R32(MAC0);
3210 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3367 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4698 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4812 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);