Lines Matching defs:qdev
8 static u32 ql_read_other_func_reg(struct ql_adapter *qdev,
17 | (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT)
19 status = ql_read_mpi_reg(qdev, register_to_read, ®_val);
27 static int ql_write_other_func_reg(struct ql_adapter *qdev,
35 | (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT)
37 status = ql_write_mpi_reg(qdev, register_to_read, reg_val);
42 static int ql_wait_other_func_reg_rdy(struct ql_adapter *qdev, u32 reg,
49 temp = ql_read_other_func_reg(qdev, reg);
62 static int ql_read_other_func_serdes_reg(struct ql_adapter *qdev, u32 reg,
68 status = ql_wait_other_func_reg_rdy(qdev, XG_SERDES_ADDR / 4,
74 ql_write_other_func_reg(qdev, XG_SERDES_ADDR/4, reg | PROC_ADDR_R);
77 status = ql_wait_other_func_reg_rdy(qdev, XG_SERDES_ADDR / 4,
83 *data = ql_read_other_func_reg(qdev, (XG_SERDES_DATA / 4));
89 static int ql_read_serdes_reg(struct ql_adapter *qdev, u32 reg, u32 * data)
94 status = ql_wait_reg_rdy(qdev, XG_SERDES_ADDR, XG_SERDES_ADDR_RDY, 0);
99 ql_write32(qdev, XG_SERDES_ADDR, reg | PROC_ADDR_R);
102 status = ql_wait_reg_rdy(qdev, XG_SERDES_ADDR, XG_SERDES_ADDR_RDY, 0);
107 *data = ql_read32(qdev, XG_SERDES_DATA);
112 static void ql_get_both_serdes(struct ql_adapter *qdev, u32 addr,
120 status = ql_read_serdes_reg(qdev, addr, direct_ptr);
128 qdev, addr, indirect_ptr);
134 static int ql_get_serdes_regs(struct ql_adapter *qdev,
147 if (qdev->func & 1) {
149 status = ql_read_other_func_serdes_reg(qdev,
157 status = ql_read_serdes_reg(qdev,
167 status = ql_read_other_func_serdes_reg(qdev,
175 status = ql_read_serdes_reg(qdev,
188 status = ql_read_serdes_reg(qdev, XG_SERDES_ADDR_STS, &temp);
195 if (qdev->func & 1)
204 if (qdev->func & 1)
212 if (qdev->func & 1) {
223 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
227 if (qdev->func & 1) {
240 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
244 if (qdev->func & 1) {
253 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
257 if (qdev->func & 1) {
268 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
272 if (qdev->func & 1) {
285 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
289 if (qdev->func & 1) {
300 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
304 if (qdev->func & 1) {
316 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
321 if (qdev->func & 1) {
333 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
338 static int ql_read_other_func_xgmac_reg(struct ql_adapter *qdev, u32 reg,
344 status = ql_wait_other_func_reg_rdy(qdev, XGMAC_ADDR / 4,
350 ql_write_other_func_reg(qdev, XGMAC_ADDR / 4, reg | XGMAC_ADDR_R);
353 status = ql_wait_other_func_reg_rdy(qdev, XGMAC_ADDR / 4,
359 *data = ql_read_other_func_reg(qdev, XGMAC_DATA / 4);
367 static int ql_get_xgmac_regs(struct ql_adapter *qdev, u32 * buf,
396 ql_read_other_func_xgmac_reg(qdev, i, buf);
398 status = ql_read_xgmac_reg(qdev, i, buf);
408 static int ql_get_ets_regs(struct ql_adapter *qdev, u32 * buf)
414 ql_write32(qdev, NIC_ETS, i << 29 | 0x08000000);
415 *buf = ql_read32(qdev, NIC_ETS);
419 ql_write32(qdev, CNA_ETS, i << 29 | 0x08000000);
420 *buf = ql_read32(qdev, CNA_ETS);
426 static void ql_get_intr_states(struct ql_adapter *qdev, u32 * buf)
430 for (i = 0; i < qdev->rx_ring_count; i++, buf++) {
431 ql_write32(qdev, INTR_EN,
432 qdev->intr_context[i].intr_read_mask);
433 *buf = ql_read32(qdev, INTR_EN);
437 static int ql_get_cam_entries(struct ql_adapter *qdev, u32 * buf)
442 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
447 status = ql_get_mac_addr_reg(qdev,
450 netif_err(qdev, drv, qdev->ndev,
459 status = ql_get_mac_addr_reg(qdev,
462 netif_err(qdev, drv, qdev->ndev,
470 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
474 static int ql_get_routing_entries(struct ql_adapter *qdev, u32 * buf)
479 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
484 status = ql_get_routing_reg(qdev, i, &value);
486 netif_err(qdev, drv, qdev->ndev,
494 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
499 static int ql_get_mpi_shadow_regs(struct ql_adapter *qdev, u32 * buf)
505 status = ql_write_mpi_reg(qdev, RISC_124,
509 status = ql_read_mpi_reg(qdev, RISC_127, buf);
518 static int ql_get_mpi_regs(struct ql_adapter *qdev, u32 * buf,
523 status = ql_read_mpi_reg(qdev, offset + i, buf);
531 static unsigned int *ql_get_probe(struct ql_adapter *qdev, u32 clock,
544 ql_write32(qdev, PRB_MX_ADDR, probe);
545 lo_val = ql_read32(qdev, PRB_MX_DATA);
551 ql_write32(qdev, PRB_MX_ADDR, probe);
552 hi_val = ql_read32(qdev, PRB_MX_DATA);
562 static int ql_get_probe_dump(struct ql_adapter *qdev, unsigned int *buf)
565 ql_write_mpi_reg(qdev, MPI_TEST_FUNC_PRB_CTL, MPI_TEST_FUNC_PRB_EN);
566 buf = ql_get_probe(qdev, PRB_MX_ADDR_SYS_CLOCK,
568 buf = ql_get_probe(qdev, PRB_MX_ADDR_PCI_CLOCK,
570 buf = ql_get_probe(qdev, PRB_MX_ADDR_XGM_CLOCK,
572 buf = ql_get_probe(qdev, PRB_MX_ADDR_FC_CLOCK,
579 static int ql_get_routing_index_registers(struct ql_adapter *qdev, u32 *buf)
587 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
600 ql_write32(qdev, RT_IDX, val);
603 result_index = ql_read32(qdev, RT_IDX);
604 result_data = ql_read32(qdev, RT_DATA);
615 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
620 static void ql_get_mac_protocol_registers(struct ql_adapter *qdev, u32 *buf)
684 ql_write32(qdev, MAC_ADDR_IDX, val);
687 result_index = ql_read32(qdev,
690 result_data = ql_read32(qdev, MAC_ADDR_DATA);
700 static void ql_get_sem_registers(struct ql_adapter *qdev, u32 *buf)
709 status = ql_read_mpi_reg(qdev, reg, ®_val);
733 * qdev structure that contains the base address of the register
737 int ql_core_dump(struct ql_adapter *qdev, struct ql_mpi_coredump *mpi_coredump)
743 netif_err(qdev, drv, qdev->ndev, "No memory available\n");
751 ql_sem_spinlock(qdev, SEM_PROC_REG_MASK);
753 status = ql_pause_mpi_risc(qdev);
755 netif_err(qdev, drv, qdev->ndev,
793 if (qdev->func & 1) {
797 ql_read32(qdev, i * sizeof(u32));
801 ql_read_other_func_reg(qdev, (i * sizeof(u32)) / 4);
803 ql_get_xgmac_regs(qdev, &mpi_coredump->xgmac2[0], 0);
804 ql_get_xgmac_regs(qdev, &mpi_coredump->xgmac1[0], 1);
809 ql_read32(qdev, i * sizeof(u32));
812 ql_read_other_func_reg(qdev, (i * sizeof(u32)) / 4);
814 ql_get_xgmac_regs(qdev, &mpi_coredump->xgmac1[0], 0);
815 ql_get_xgmac_regs(qdev, &mpi_coredump->xgmac2[0], 1);
915 status = ql_get_serdes_regs(qdev, mpi_coredump);
917 netif_err(qdev, drv, qdev->ndev,
931 status = ql_get_mpi_regs(qdev, &mpi_coredump->mpi_core_regs[0],
936 status = ql_get_mpi_shadow_regs(qdev,
947 status = ql_get_mpi_regs(qdev, &mpi_coredump->test_logic_regs[0],
958 status = ql_get_mpi_regs(qdev, &mpi_coredump->rmii_regs[0],
969 status = ql_get_mpi_regs(qdev, &mpi_coredump->fcmac1_regs[0],
982 status = ql_get_mpi_regs(qdev, &mpi_coredump->fcmac2_regs[0],
993 status = ql_get_mpi_regs(qdev, &mpi_coredump->fc1_mbx_regs[0],
1004 status = ql_get_mpi_regs(qdev, &mpi_coredump->ide_regs[0],
1015 status = ql_get_mpi_regs(qdev, &mpi_coredump->nic1_mbx_regs[0],
1026 status = ql_get_mpi_regs(qdev, &mpi_coredump->smbus_regs[0],
1037 status = ql_get_mpi_regs(qdev, &mpi_coredump->fc2_mbx_regs[0],
1048 status = ql_get_mpi_regs(qdev, &mpi_coredump->nic2_mbx_regs[0],
1059 status = ql_get_mpi_regs(qdev, &mpi_coredump->i2c_regs[0],
1070 status = ql_get_mpi_regs(qdev, &mpi_coredump->memc_regs[0],
1081 status = ql_get_mpi_regs(qdev, &mpi_coredump->pbus_regs[0],
1092 status = ql_get_mpi_regs(qdev, &mpi_coredump->mde_regs[0],
1102 mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count;
1103 mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count;
1104 mpi_coredump->misc_nic_info.intr_count = qdev->intr_count;
1105 mpi_coredump->misc_nic_info.function = qdev->func;
1114 ql_get_intr_states(qdev, &mpi_coredump->intr_states[0]);
1121 status = ql_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]);
1130 status = ql_get_routing_entries(qdev,
1141 status = ql_get_ets_regs(qdev, &mpi_coredump->ets[0]);
1150 ql_get_probe_dump(qdev, &mpi_coredump->probe_dump[0]);
1157 status = ql_get_routing_index_registers(qdev,
1167 ql_get_mac_protocol_registers(qdev, &mpi_coredump->mac_prot_regs[0]);
1175 ql_get_sem_registers(qdev, &mpi_coredump->sem_regs[0]);
1178 ql_write_mpi_reg(qdev, MPI_TEST_FUNC_RST_STS, MPI_TEST_FUNC_RST_FRC);
1181 status = ql_unpause_mpi_risc(qdev);
1183 netif_err(qdev, drv, qdev->ndev,
1189 status = ql_hard_reset_mpi_risc(qdev);
1191 netif_err(qdev, drv, qdev->ndev,
1201 status = ql_dump_risc_ram_area(qdev, &mpi_coredump->code_ram[0],
1204 netif_err(qdev, drv, qdev->ndev,
1216 status = ql_dump_risc_ram_area(qdev, &mpi_coredump->memc_ram[0],
1219 netif_err(qdev, drv, qdev->ndev,
1225 ql_sem_unlock(qdev, SEM_PROC_REG_MASK); /* does flush too */
1230 static void ql_get_core_dump(struct ql_adapter *qdev)
1232 if (!ql_own_firmware(qdev)) {
1233 netif_err(qdev, drv, qdev->ndev, "Don't own firmware!\n");
1237 if (!netif_running(qdev->ndev)) {
1238 netif_err(qdev, ifup, qdev->ndev,
1242 ql_queue_fw_error(qdev);
1245 void ql_gen_reg_dump(struct ql_adapter *qdev,
1268 mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count;
1269 mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count;
1270 mpi_coredump->misc_nic_info.intr_count = qdev->intr_count;
1271 mpi_coredump->misc_nic_info.function = qdev->func;
1281 mpi_coredump->nic_regs[i] = ql_read32(qdev, i * sizeof(u32));
1290 ql_get_intr_states(qdev, &mpi_coredump->intr_states[0]);
1297 status = ql_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]);
1306 status = ql_get_routing_entries(qdev,
1317 status = ql_get_ets_regs(qdev, &mpi_coredump->ets[0]);
1321 if (test_bit(QL_FRC_COREDUMP, &qdev->flags))
1322 ql_get_core_dump(qdev);
1328 struct ql_adapter *qdev =
1334 tmp = (u32 *)qdev->mpi_coredump;
1335 netif_printk(qdev, drv, KERN_DEBUG, qdev->ndev,
1354 static void ql_dump_intr_states(struct ql_adapter *qdev)
1358 for (i = 0; i < qdev->intr_count; i++) {
1359 ql_write32(qdev, INTR_EN, qdev->intr_context[i].intr_read_mask);
1360 value = ql_read32(qdev, INTR_EN);
1362 qdev->ndev->name, i,
1367 #define DUMP_XGMAC(qdev, reg) \
1370 ql_read_xgmac_reg(qdev, reg, &data); \
1371 pr_err("%s: %s = 0x%.08x\n", qdev->ndev->name, #reg, data); \
1374 void ql_dump_xgmac_control_regs(struct ql_adapter *qdev)
1376 if (ql_sem_spinlock(qdev, qdev->xg_sem_mask)) {
1380 DUMP_XGMAC(qdev, PAUSE_SRC_LO);
1381 DUMP_XGMAC(qdev, PAUSE_SRC_HI);
1382 DUMP_XGMAC(qdev, GLOBAL_CFG);
1383 DUMP_XGMAC(qdev, TX_CFG);
1384 DUMP_XGMAC(qdev, RX_CFG);
1385 DUMP_XGMAC(qdev, FLOW_CTL);
1386 DUMP_XGMAC(qdev, PAUSE_OPCODE);
1387 DUMP_XGMAC(qdev, PAUSE_TIMER);
1388 DUMP_XGMAC(qdev, PAUSE_FRM_DEST_LO);
1389 DUMP_XGMAC(qdev, PAUSE_FRM_DEST_HI);
1390 DUMP_XGMAC(qdev, MAC_TX_PARAMS);
1391 DUMP_XGMAC(qdev, MAC_RX_PARAMS);
1392 DUMP_XGMAC(qdev, MAC_SYS_INT);
1393 DUMP_XGMAC(qdev, MAC_SYS_INT_MASK);
1394 DUMP_XGMAC(qdev, MAC_MGMT_INT);
1395 DUMP_XGMAC(qdev, MAC_MGMT_IN_MASK);
1396 DUMP_XGMAC(qdev, EXT_ARB_MODE);
1397 ql_sem_unlock(qdev, qdev->xg_sem_mask);
1400 static void ql_dump_ets_regs(struct ql_adapter *qdev)
1404 static void ql_dump_cam_entries(struct ql_adapter *qdev)
1409 i = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1413 if (ql_get_mac_addr_reg(qdev, MAC_ADDR_TYPE_CAM_MAC, i, value)) {
1420 qdev->ndev->name, i, value[1], value[0],
1426 (qdev, MAC_ADDR_TYPE_MULTI_MAC, i, value)) {
1433 qdev->ndev->name, i, value[1], value[0]);
1436 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1439 void ql_dump_routing_entries(struct ql_adapter *qdev)
1443 i = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
1448 if (ql_get_routing_reg(qdev, i, &value)) {
1455 qdev->ndev->name, i, value);
1458 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
1461 #define DUMP_REG(qdev, reg) \
1462 pr_err("%-32s= 0x%x\n", #reg, ql_read32(qdev, reg))
1464 void ql_dump_regs(struct ql_adapter *qdev)
1466 pr_err("reg dump for function #%d\n", qdev->func);
1467 DUMP_REG(qdev, SYS);
1468 DUMP_REG(qdev, RST_FO);
1469 DUMP_REG(qdev, FSC);
1470 DUMP_REG(qdev, CSR);
1471 DUMP_REG(qdev, ICB_RID);
1472 DUMP_REG(qdev, ICB_L);
1473 DUMP_REG(qdev, ICB_H);
1474 DUMP_REG(qdev, CFG);
1475 DUMP_REG(qdev, BIOS_ADDR);
1476 DUMP_REG(qdev, STS);
1477 DUMP_REG(qdev, INTR_EN);
1478 DUMP_REG(qdev, INTR_MASK);
1479 DUMP_REG(qdev, ISR1);
1480 DUMP_REG(qdev, ISR2);
1481 DUMP_REG(qdev, ISR3);
1482 DUMP_REG(qdev, ISR4);
1483 DUMP_REG(qdev, REV_ID);
1484 DUMP_REG(qdev, FRC_ECC_ERR);
1485 DUMP_REG(qdev, ERR_STS);
1486 DUMP_REG(qdev, RAM_DBG_ADDR);
1487 DUMP_REG(qdev, RAM_DBG_DATA);
1488 DUMP_REG(qdev, ECC_ERR_CNT);
1489 DUMP_REG(qdev, SEM);
1490 DUMP_REG(qdev, GPIO_1);
1491 DUMP_REG(qdev, GPIO_2);
1492 DUMP_REG(qdev, GPIO_3);
1493 DUMP_REG(qdev, XGMAC_ADDR);
1494 DUMP_REG(qdev, XGMAC_DATA);
1495 DUMP_REG(qdev, NIC_ETS);
1496 DUMP_REG(qdev, CNA_ETS);
1497 DUMP_REG(qdev, FLASH_ADDR);
1498 DUMP_REG(qdev, FLASH_DATA);
1499 DUMP_REG(qdev, CQ_STOP);
1500 DUMP_REG(qdev, PAGE_TBL_RID);
1501 DUMP_REG(qdev, WQ_PAGE_TBL_LO);
1502 DUMP_REG(qdev, WQ_PAGE_TBL_HI);
1503 DUMP_REG(qdev, CQ_PAGE_TBL_LO);
1504 DUMP_REG(qdev, CQ_PAGE_TBL_HI);
1505 DUMP_REG(qdev, COS_DFLT_CQ1);
1506 DUMP_REG(qdev, COS_DFLT_CQ2);
1507 DUMP_REG(qdev, SPLT_HDR);
1508 DUMP_REG(qdev, FC_PAUSE_THRES);
1509 DUMP_REG(qdev, NIC_PAUSE_THRES);
1510 DUMP_REG(qdev, FC_ETHERTYPE);
1511 DUMP_REG(qdev, FC_RCV_CFG);
1512 DUMP_REG(qdev, NIC_RCV_CFG);
1513 DUMP_REG(qdev, FC_COS_TAGS);
1514 DUMP_REG(qdev, NIC_COS_TAGS);
1515 DUMP_REG(qdev, MGMT_RCV_CFG);
1516 DUMP_REG(qdev, XG_SERDES_ADDR);
1517 DUMP_REG(qdev, XG_SERDES_DATA);
1518 DUMP_REG(qdev, PRB_MX_ADDR);
1519 DUMP_REG(qdev, PRB_MX_DATA);
1520 ql_dump_intr_states(qdev);
1521 ql_dump_xgmac_control_regs(qdev);
1522 ql_dump_ets_regs(qdev);
1523 ql_dump_cam_entries(qdev);
1524 ql_dump_routing_entries(qdev);
1530 #define DUMP_STAT(qdev, stat) \
1531 pr_err("%s = %ld\n", #stat, (unsigned long)qdev->nic_stats.stat)
1533 void ql_dump_stat(struct ql_adapter *qdev)
1536 DUMP_STAT(qdev, tx_pkts);
1537 DUMP_STAT(qdev, tx_bytes);
1538 DUMP_STAT(qdev, tx_mcast_pkts);
1539 DUMP_STAT(qdev, tx_bcast_pkts);
1540 DUMP_STAT(qdev, tx_ucast_pkts);
1541 DUMP_STAT(qdev, tx_ctl_pkts);
1542 DUMP_STAT(qdev, tx_pause_pkts);
1543 DUMP_STAT(qdev, tx_64_pkt);
1544 DUMP_STAT(qdev, tx_65_to_127_pkt);
1545 DUMP_STAT(qdev, tx_128_to_255_pkt);
1546 DUMP_STAT(qdev, tx_256_511_pkt);
1547 DUMP_STAT(qdev, tx_512_to_1023_pkt);
1548 DUMP_STAT(qdev, tx_1024_to_1518_pkt);
1549 DUMP_STAT(qdev, tx_1519_to_max_pkt);
1550 DUMP_STAT(qdev, tx_undersize_pkt);
1551 DUMP_STAT(qdev, tx_oversize_pkt);
1552 DUMP_STAT(qdev, rx_bytes);
1553 DUMP_STAT(qdev, rx_bytes_ok);
1554 DUMP_STAT(qdev, rx_pkts);
1555 DUMP_STAT(qdev, rx_pkts_ok);
1556 DUMP_STAT(qdev, rx_bcast_pkts);
1557 DUMP_STAT(qdev, rx_mcast_pkts);
1558 DUMP_STAT(qdev, rx_ucast_pkts);
1559 DUMP_STAT(qdev, rx_undersize_pkts);
1560 DUMP_STAT(qdev, rx_oversize_pkts);
1561 DUMP_STAT(qdev, rx_jabber_pkts);
1562 DUMP_STAT(qdev, rx_undersize_fcerr_pkts);
1563 DUMP_STAT(qdev, rx_drop_events);
1564 DUMP_STAT(qdev, rx_fcerr_pkts);
1565 DUMP_STAT(qdev, rx_align_err);
1566 DUMP_STAT(qdev, rx_symbol_err);
1567 DUMP_STAT(qdev, rx_mac_err);
1568 DUMP_STAT(qdev, rx_ctl_pkts);
1569 DUMP_STAT(qdev, rx_pause_pkts);
1570 DUMP_STAT(qdev, rx_64_pkts);
1571 DUMP_STAT(qdev, rx_65_to_127_pkts);
1572 DUMP_STAT(qdev, rx_128_255_pkts);
1573 DUMP_STAT(qdev, rx_256_511_pkts);
1574 DUMP_STAT(qdev, rx_512_to_1023_pkts);
1575 DUMP_STAT(qdev, rx_1024_to_1518_pkts);
1576 DUMP_STAT(qdev, rx_1519_to_max_pkts);
1577 DUMP_STAT(qdev, rx_len_err_pkts);
1583 #define DUMP_QDEV_FIELD(qdev, type, field) \
1584 pr_err("qdev->%-24s = " type "\n", #field, qdev->field)
1585 #define DUMP_QDEV_DMA_FIELD(qdev, field) \
1586 pr_err("qdev->%-24s = %llx\n", #field, (unsigned long long)qdev->field)
1587 #define DUMP_QDEV_ARRAY(qdev, type, array, index, field) \
1589 #array, index, #field, qdev->array[index].field);
1590 void ql_dump_qdev(struct ql_adapter *qdev)
1593 DUMP_QDEV_FIELD(qdev, "%lx", flags);
1594 DUMP_QDEV_FIELD(qdev, "%p", vlgrp);
1595 DUMP_QDEV_FIELD(qdev, "%p", pdev);
1596 DUMP_QDEV_FIELD(qdev, "%p", ndev);
1597 DUMP_QDEV_FIELD(qdev, "%d", chip_rev_id);
1598 DUMP_QDEV_FIELD(qdev, "%p", reg_base);
1599 DUMP_QDEV_FIELD(qdev, "%p", doorbell_area);
1600 DUMP_QDEV_FIELD(qdev, "%d", doorbell_area_size);
1601 DUMP_QDEV_FIELD(qdev, "%x", msg_enable);
1602 DUMP_QDEV_FIELD(qdev, "%p", rx_ring_shadow_reg_area);
1603 DUMP_QDEV_DMA_FIELD(qdev, rx_ring_shadow_reg_dma);
1604 DUMP_QDEV_FIELD(qdev, "%p", tx_ring_shadow_reg_area);
1605 DUMP_QDEV_DMA_FIELD(qdev, tx_ring_shadow_reg_dma);
1606 DUMP_QDEV_FIELD(qdev, "%d", intr_count);
1607 if (qdev->msi_x_entry)
1608 for (i = 0; i < qdev->intr_count; i++) {
1609 DUMP_QDEV_ARRAY(qdev, "%d", msi_x_entry, i, vector);
1610 DUMP_QDEV_ARRAY(qdev, "%d", msi_x_entry, i, entry);
1612 for (i = 0; i < qdev->intr_count; i++) {
1613 DUMP_QDEV_ARRAY(qdev, "%p", intr_context, i, qdev);
1614 DUMP_QDEV_ARRAY(qdev, "%d", intr_context, i, intr);
1615 DUMP_QDEV_ARRAY(qdev, "%d", intr_context, i, hooked);
1616 DUMP_QDEV_ARRAY(qdev, "0x%08x", intr_context, i, intr_en_mask);
1617 DUMP_QDEV_ARRAY(qdev, "0x%08x", intr_context, i, intr_dis_mask);
1618 DUMP_QDEV_ARRAY(qdev, "0x%08x", intr_context, i, intr_read_mask);
1620 DUMP_QDEV_FIELD(qdev, "%d", tx_ring_count);
1621 DUMP_QDEV_FIELD(qdev, "%d", rx_ring_count);
1622 DUMP_QDEV_FIELD(qdev, "%d", ring_mem_size);
1623 DUMP_QDEV_FIELD(qdev, "%p", ring_mem);
1624 DUMP_QDEV_FIELD(qdev, "%d", intr_count);
1625 DUMP_QDEV_FIELD(qdev, "%p", tx_ring);
1626 DUMP_QDEV_FIELD(qdev, "%d", rss_ring_count);
1627 DUMP_QDEV_FIELD(qdev, "%p", rx_ring);
1628 DUMP_QDEV_FIELD(qdev, "%d", default_rx_queue);
1629 DUMP_QDEV_FIELD(qdev, "0x%08x", xg_sem_mask);
1630 DUMP_QDEV_FIELD(qdev, "0x%08x", port_link_up);
1631 DUMP_QDEV_FIELD(qdev, "0x%08x", port_init);
1798 pr_err("rx_ring->qdev = %p\n", rx_ring->qdev);
1801 void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id)
1813 if (ql_write_cfg(qdev, ptr, size, bit, q_id)) {
2010 void ql_dump_all(struct ql_adapter *qdev)
2014 QL_DUMP_REGS(qdev);
2015 QL_DUMP_QDEV(qdev);
2016 for (i = 0; i < qdev->tx_ring_count; i++) {
2017 QL_DUMP_TX_RING(&qdev->tx_ring[i]);
2018 QL_DUMP_WQICB((struct wqicb *)&qdev->tx_ring[i]);
2020 for (i = 0; i < qdev->rx_ring_count; i++) {
2021 QL_DUMP_RX_RING(&qdev->rx_ring[i]);
2022 QL_DUMP_CQICB((struct cqicb *)&qdev->rx_ring[i]);