Lines Matching refs:FZC_DMC
19 #define FZC_DMC 0x680000UL
1518 #define RX_DMA_CK_DIV (FZC_DMC + 0x00000UL)
1521 #define DEF_RDC(IDX) (FZC_DMC + 0x00008UL + (IDX) * 0x8UL)
1524 #define PT_DRR_WT(IDX) (FZC_DMC + 0x00028UL + (IDX) * 0x8UL)
1530 #define PT_USE(IDX) (FZC_DMC + 0x00048UL + (IDX) * 0x8UL)
1533 #define RED_RAN_INIT (FZC_DMC + 0x00068UL)
1537 #define RX_ADDR_MD (FZC_DMC + 0x00070UL)
1542 #define RDMC_PRE_PAR_ERR (FZC_DMC + 0x00078UL)
1547 #define RDMC_SHA_PAR_ERR (FZC_DMC + 0x00080UL)
1552 #define RDMC_MEM_ADDR (FZC_DMC + 0x00088UL)
1556 #define RDMC_MEM_DAT0 (FZC_DMC + 0x00090UL)
1559 #define RDMC_MEM_DAT1 (FZC_DMC + 0x00098UL)
1562 #define RDMC_MEM_DAT2 (FZC_DMC + 0x000a0UL)
1565 #define RDMC_MEM_DAT3 (FZC_DMC + 0x000a8UL)
1568 #define RDMC_MEM_DAT4 (FZC_DMC + 0x000b0UL)
1571 #define RX_CTL_DAT_FIFO_STAT (FZC_DMC + 0x000b8UL)
1576 #define RX_CTL_DAT_FIFO_MASK (FZC_DMC + 0x000c0UL)
1581 #define RDMC_TRAINING_VECTOR (FZC_DMC + 0x000c8UL)
1584 #define RX_CTL_DAT_FIFO_STAT_DBG (FZC_DMC + 0x000d0UL)
1594 #define RX_LOG_PAGE_VLD(IDX) (FZC_DMC + 0x20000UL + (IDX) * 0x40UL)
1600 #define RX_LOG_MASK1(IDX) (FZC_DMC + 0x20008UL + (IDX) * 0x40UL)
1603 #define RX_LOG_VAL1(IDX) (FZC_DMC + 0x20010UL + (IDX) * 0x40UL)
1606 #define RX_LOG_MASK2(IDX) (FZC_DMC + 0x20018UL + (IDX) * 0x40UL)
1609 #define RX_LOG_VAL2(IDX) (FZC_DMC + 0x20020UL + (IDX) * 0x40UL)
1612 #define RX_LOG_PAGE_RELO1(IDX) (FZC_DMC + 0x20028UL + (IDX) * 0x40UL)
1615 #define RX_LOG_PAGE_RELO2(IDX) (FZC_DMC + 0x20030UL + (IDX) * 0x40UL)
1618 #define RX_LOG_PAGE_HDL(IDX) (FZC_DMC + 0x20038UL + (IDX) * 0x40UL)
1621 #define TX_LOG_PAGE_VLD(IDX) (FZC_DMC + 0x40000UL + (IDX) * 0x200UL)
1627 #define TX_LOG_MASK1(IDX) (FZC_DMC + 0x40008UL + (IDX) * 0x200UL)
1630 #define TX_LOG_VAL1(IDX) (FZC_DMC + 0x40010UL + (IDX) * 0x200UL)
1633 #define TX_LOG_MASK2(IDX) (FZC_DMC + 0x40018UL + (IDX) * 0x200UL)
1636 #define TX_LOG_VAL2(IDX) (FZC_DMC + 0x40020UL + (IDX) * 0x200UL)
1639 #define TX_LOG_PAGE_RELO1(IDX) (FZC_DMC + 0x40028UL + (IDX) * 0x200UL)
1642 #define TX_LOG_PAGE_RELO2(IDX) (FZC_DMC + 0x40030UL + (IDX) * 0x200UL)
1645 #define TX_LOG_PAGE_HDL(IDX) (FZC_DMC + 0x40038UL + (IDX) * 0x200UL)
1648 #define TX_ADDR_MD (FZC_DMC + 0x45000UL)
1651 #define RDC_RED_PARA(IDX) (FZC_DMC + 0x30000UL + (IDX) * 0x40UL)
1661 #define RED_DIS_CNT(IDX) (FZC_DMC + 0x30008UL + (IDX) * 0x40UL)