Lines Matching defs:CSR0
140 #define CSR0 0x00
150 #define writedatareg(val) { writereg(val,CSR0); }
251 writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */
266 outw(CSR0,PORT+L_ADDRREG); /* switch back to CSR0 */
442 if( (j=readreg(CSR0)) != 0x4) {
494 if(readreg(CSR0) & CSR0_IDON)
516 writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */
555 writereg(CSR0_CLRALL|CSR0_STOP,CSR0);
571 writereg(CSR0_INIT,CSR0); /* this changes L_ADDRREG to CSR0 */
790 if( (i=readreg(CSR0) ) != 0x4)
836 * ni65_set_lance_mem() sets L_ADDRREG to CSR0
837 * NOW, WE WILL NEVER CHANGE THE L_ADDRREG, CSR0 IS ALWAYS SELECTED