Lines Matching defs:dev_cap
145 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
150 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
156 if (dev_cap->min_page_sz > PAGE_SIZE) {
159 dev_cap->min_page_sz, PAGE_SIZE);
162 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
165 dev_cap->num_ports, MLX4_MAX_PORTS);
169 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
172 dev_cap->uar_size,
177 dev->caps.num_ports = dev_cap->num_ports;
179 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
180 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
181 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
182 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
183 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
184 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
185 dev->caps.def_mac[i] = dev_cap->def_mac[i];
186 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
189 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
190 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
191 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
192 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
193 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
194 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
195 dev->caps.max_wqes = dev_cap->max_qp_sz;
196 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
197 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
198 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
199 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
200 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
201 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
208 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
209 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
210 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
212 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
214 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
215 dev->caps.reserved_uars = dev_cap->reserved_uars;
216 dev->caps.reserved_pds = dev_cap->reserved_pds;
217 dev->caps.mtt_entry_sz = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
218 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
219 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
220 dev->caps.flags = dev_cap->flags;
221 dev->caps.bmme_flags = dev_cap->bmme_flags;
222 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
223 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
224 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
239 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
240 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
245 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
246 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
255 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
493 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
523 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
530 init_hca->eqc_base, dev_cap->eqc_entry_sz,
561 dev_cap->dmpt_entry_sz,
571 dev_cap->qpc_entry_sz,
582 dev_cap->aux_entry_sz,
593 dev_cap->altc_entry_sz,
604 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
615 dev_cap->cqc_entry_sz,
625 dev_cap->srq_entry_sz,
727 struct mlx4_dev_cap dev_cap;
755 err = mlx4_dev_cap(dev, &dev_cap);
763 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
771 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);