Lines Matching refs:ull
88 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
89 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
90 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
91 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
92 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
93 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
94 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
95 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
96 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
97 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
98 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
99 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
100 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
101 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
102 (1ull << MLX4_EVENT_TYPE_CMD))