Lines Matching refs:eth
101 mace->eth.mac_addr = macaddr;
108 while ((___rval = mace->eth.phy_data) & MDIO_BUSY) { \
116 mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
118 mace->eth.phy_trans_go = 1;
187 mace->eth.mac_ctrl = priv->mac_ctrl;
196 mace->eth.mac_ctrl = priv->mac_ctrl;
210 mace->eth.tx_ring_base = priv->tx_ring_dma;
231 mace->eth.rx_fifo = priv->rx_ring_dmas[i];
269 mace->eth.mac_ctrl = SGI_MAC_RESET;
271 mace->eth.mac_ctrl = 0;
288 mace->eth.mac_ctrl = priv->mac_ctrl;
296 mace->eth.dma_ctrl = priv->dma_ctrl;
335 mace->eth.dma_ctrl = priv->dma_ctrl;
359 mace->eth.dma_ctrl = priv->dma_ctrl;
379 mace->eth.dma_ctrl = priv->dma_ctrl;
449 mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
455 mace->eth.dma_ctrl = priv->dma_ctrl;
456 mace->eth.int_stat = METH_INT_RX_THRESHOLD;
478 mace->eth.dma_ctrl = priv->dma_ctrl;
526 mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
549 mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
554 mace->eth.dma_ctrl = priv->dma_ctrl;
558 mace->eth.int_stat = METH_INT_ERROR;
570 status = mace->eth.int_stat;
589 status = mace->eth.int_stat;
683 mace->eth.tx_info = priv->tx_write;
698 mace->eth.dma_ctrl = priv->dma_ctrl;
711 mace->eth.dma_ctrl = priv->dma_ctrl;
744 mace->eth.dma_ctrl = priv->dma_ctrl;
794 dev->base_addr = (unsigned long)&mace->eth;
808 dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));