Lines Matching defs:rx_cfg
1244 * @rx_cfg: Cached receive control settings.
1283 u32 rx_cfg;
3221 u32 rx_cfg;
3224 rx_cfg = hw->rx_cfg;
3227 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
3229 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
3235 if (rx_cfg != hw->rx_cfg)
3236 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3795 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3797 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3800 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3803 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3805 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3904 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3928 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
4223 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
4225 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
4244 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
4246 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
5047 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
5243 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
5448 hw->rx_cfg |= DMA_RX_ERROR;
5451 hw->rx_cfg &= ~DMA_RX_ERROR;
6350 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
6598 return hw->rx_cfg &
6618 u32 new_setting = hw->rx_cfg;
6630 if (new_setting != hw->rx_cfg) {
6631 hw->rx_cfg = new_setting;
6633 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);