Lines Matching refs:JME_MISC
463 JME_MISC = 0x0800,
508 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
509 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
510 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
511 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
512 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
513 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
514 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
515 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
516 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
517 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
518 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
519 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
520 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
521 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
522 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
523 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */