Lines Matching defs:value
30 u32 value;
40 * Read initial value.
42 value = ixp2000_reg_read(IXP2000_MSF_CLK_CNTRL);
47 value |= 0x0000f0f0;
48 ixp2000_reg_write(IXP2000_MSF_CLK_CNTRL, value);
53 value &= ~0x03000000;
54 value |= (rx_dual_clock << 24) | (tx_dual_clock << 25);
59 value &= ~0x00ff0000;
60 value |= mp->rxclk01_multiplier << 16;
61 value |= mp->rxclk23_multiplier << 18;
62 value |= mp->txclk01_multiplier << 20;
63 value |= mp->txclk23_multiplier << 22;
66 * And write value.
68 ixp2000_reg_write(IXP2000_MSF_CLK_CNTRL, value);
73 value &= ~(0x00005000 | rx_dual_clock << 13 | tx_dual_clock << 15);
74 ixp2000_reg_write(IXP2000_MSF_CLK_CNTRL, value);
79 value &= ~(0x00000050 | rx_dual_clock << 5 | tx_dual_clock << 7);
80 ixp2000_reg_write(IXP2000_MSF_CLK_CNTRL, value);
151 u32 value;
153 value = ixp2000_reg_read(IXP2000_MSF_RX_CONTROL) & 0x0fffffff;
154 value |= ixp2400_msf_valid_channels(mp->rx_mode) << 28;
155 ixp2000_reg_write(IXP2000_MSF_RX_CONTROL, value);
160 u32 value;
162 value = ixp2000_reg_read(IXP2000_MSF_TX_CONTROL) & 0x0fffffff;
163 value |= ixp2400_msf_valid_channels(mp->tx_mode) << 28;
164 ixp2000_reg_write(IXP2000_MSF_TX_CONTROL, value);
170 u32 value;
181 value = ixp2000_reg_read(IXP2000_RESET0);
182 ixp2000_reg_write(IXP2000_RESET0, value | 0x80);
183 ixp2000_reg_write(IXP2000_RESET0, value & ~0x80);