Lines Matching refs:hw
37 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
38 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
40 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
44 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
48 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
50 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
51 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
52 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
54 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
58 * @hw: pointer to hardware structure
65 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
70 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
73 hw->phy.ops.identify(hw);
76 hw->mac.ops.clear_vfta(hw);
79 hw->mac.ops.clear_hw_cntrs(hw);
82 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
84 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
85 IXGBE_WRITE_FLUSH(hw);
88 ixgbe_setup_fc(hw, 0);
91 hw->adapter_stopped = false;
98 * @hw: pointer to hardware structure
106 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
111 status = hw->mac.ops.reset_hw(hw);
115 status = hw->mac.ops.start_hw(hw);
123 * @hw: pointer to hardware structure
128 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
132 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
133 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
134 IXGBE_READ_REG(hw, IXGBE_ERRBC);
135 IXGBE_READ_REG(hw, IXGBE_MSPDC);
137 IXGBE_READ_REG(hw, IXGBE_MPC(i));
139 IXGBE_READ_REG(hw, IXGBE_MLFC);
140 IXGBE_READ_REG(hw, IXGBE_MRFC);
141 IXGBE_READ_REG(hw, IXGBE_RLEC);
142 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
143 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
144 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
145 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
148 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
149 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
150 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
151 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
154 IXGBE_READ_REG(hw, IXGBE_PRC64);
155 IXGBE_READ_REG(hw, IXGBE_PRC127);
156 IXGBE_READ_REG(hw, IXGBE_PRC255);
157 IXGBE_READ_REG(hw, IXGBE_PRC511);
158 IXGBE_READ_REG(hw, IXGBE_PRC1023);
159 IXGBE_READ_REG(hw, IXGBE_PRC1522);
160 IXGBE_READ_REG(hw, IXGBE_GPRC);
161 IXGBE_READ_REG(hw, IXGBE_BPRC);
162 IXGBE_READ_REG(hw, IXGBE_MPRC);
163 IXGBE_READ_REG(hw, IXGBE_GPTC);
164 IXGBE_READ_REG(hw, IXGBE_GORCL);
165 IXGBE_READ_REG(hw, IXGBE_GORCH);
166 IXGBE_READ_REG(hw, IXGBE_GOTCL);
167 IXGBE_READ_REG(hw, IXGBE_GOTCH);
169 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
170 IXGBE_READ_REG(hw, IXGBE_RUC);
171 IXGBE_READ_REG(hw, IXGBE_RFC);
172 IXGBE_READ_REG(hw, IXGBE_ROC);
173 IXGBE_READ_REG(hw, IXGBE_RJC);
174 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
175 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
176 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
177 IXGBE_READ_REG(hw, IXGBE_TORL);
178 IXGBE_READ_REG(hw, IXGBE_TORH);
179 IXGBE_READ_REG(hw, IXGBE_TPR);
180 IXGBE_READ_REG(hw, IXGBE_TPT);
181 IXGBE_READ_REG(hw, IXGBE_PTC64);
182 IXGBE_READ_REG(hw, IXGBE_PTC127);
183 IXGBE_READ_REG(hw, IXGBE_PTC255);
184 IXGBE_READ_REG(hw, IXGBE_PTC511);
185 IXGBE_READ_REG(hw, IXGBE_PTC1023);
186 IXGBE_READ_REG(hw, IXGBE_PTC1522);
187 IXGBE_READ_REG(hw, IXGBE_MPTC);
188 IXGBE_READ_REG(hw, IXGBE_BPTC);
190 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
191 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
192 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
193 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
201 * @hw: pointer to hardware structure
206 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
211 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
213 hw_dbg(hw, "NVM Read Error\n");
218 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
220 hw_dbg(hw, "NVM Read Error\n");
230 * @hw: pointer to hardware structure
237 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
243 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
244 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
257 * @hw: pointer to hardware structure
261 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
263 struct ixgbe_adapter *adapter = hw->back;
264 struct ixgbe_mac_info *mac = &hw->mac;
267 hw->bus.type = ixgbe_bus_type_pci_express;
275 hw->bus.width = ixgbe_bus_width_pcie_x1;
278 hw->bus.width = ixgbe_bus_width_pcie_x2;
281 hw->bus.width = ixgbe_bus_width_pcie_x4;
284 hw->bus.width = ixgbe_bus_width_pcie_x8;
287 hw->bus.width = ixgbe_bus_width_unknown;
293 hw->bus.speed = ixgbe_bus_speed_2500;
296 hw->bus.speed = ixgbe_bus_speed_5000;
299 hw->bus.speed = ixgbe_bus_speed_unknown;
303 mac->ops.set_lan_id(hw);
310 * @hw: pointer to the HW structure
315 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
317 struct ixgbe_bus_info *bus = &hw->bus;
320 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
325 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
332 * @hw: pointer to hardware structure
339 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
349 hw->adapter_stopped = true;
352 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
354 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
355 IXGBE_WRITE_FLUSH(hw);
359 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
362 IXGBE_READ_REG(hw, IXGBE_EICR);
365 number_of_queues = hw->mac.max_tx_queues;
367 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
370 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
378 if (ixgbe_disable_pcie_master(hw) != 0)
379 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
386 * @hw: pointer to hardware structure
389 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
391 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
396 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
397 IXGBE_WRITE_FLUSH(hw);
404 * @hw: pointer to hardware structure
407 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
409 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
414 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
415 IXGBE_WRITE_FLUSH(hw);
422 * @hw: pointer to hardware structure
427 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
429 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
443 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
461 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
471 * @hw: pointer to hardware structure
478 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
483 hw->eeprom.ops.init_params(hw);
485 if (offset >= hw->eeprom.word_size) {
491 status = ixgbe_acquire_eeprom(hw);
494 if (ixgbe_ready_eeprom(hw) != 0) {
495 ixgbe_release_eeprom(hw);
501 ixgbe_standby_eeprom(hw);
504 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
507 ixgbe_standby_eeprom(hw);
513 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
517 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
519 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
520 hw->eeprom.address_bits);
524 ixgbe_shift_out_eeprom_bits(hw, data, 16);
525 ixgbe_standby_eeprom(hw);
527 msleep(hw->eeprom.semaphore_delay);
529 ixgbe_release_eeprom(hw);
538 * @hw: pointer to hardware structure
544 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
551 hw->eeprom.ops.init_params(hw);
553 if (offset >= hw->eeprom.word_size) {
559 status = ixgbe_acquire_eeprom(hw);
562 if (ixgbe_ready_eeprom(hw) != 0) {
563 ixgbe_release_eeprom(hw);
569 ixgbe_standby_eeprom(hw);
575 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
579 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
581 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
582 hw->eeprom.address_bits);
585 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
589 ixgbe_release_eeprom(hw);
598 * @hw: pointer to hardware structure
604 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
609 hw->eeprom.ops.init_params(hw);
611 if (offset >= hw->eeprom.word_size) {
619 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
620 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
623 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
626 hw_dbg(hw, "Eeprom read timed out\n");
634 * @hw: pointer to hardware structure
640 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
648 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
650 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
663 * @hw: pointer to hardware structure
668 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
674 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
678 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
682 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
685 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
694 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
695 hw_dbg(hw, "Could not acquire EEPROM grant\n");
697 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
706 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
707 IXGBE_WRITE_FLUSH(hw);
715 * @hw: pointer to hardware structure
719 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
727 timeout = hw->eeprom.word_size + 1;
735 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
746 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
750 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
756 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
768 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
770 ixgbe_release_eeprom_semaphore(hw);
780 * @hw: pointer to hardware structure
784 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
788 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
792 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
793 IXGBE_WRITE_FLUSH(hw);
798 * @hw: pointer to hardware structure
800 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
813 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
815 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
820 ixgbe_standby_eeprom(hw);
828 hw_dbg(hw, "SPI EEPROM Status error\n");
837 * @hw: pointer to hardware structure
839 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
843 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
847 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
848 IXGBE_WRITE_FLUSH(hw);
851 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
852 IXGBE_WRITE_FLUSH(hw);
858 * @hw: pointer to hardware structure
862 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
869 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
890 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
891 IXGBE_WRITE_FLUSH(hw);
895 ixgbe_raise_eeprom_clk(hw, &eec);
896 ixgbe_lower_eeprom_clk(hw, &eec);
907 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
908 IXGBE_WRITE_FLUSH(hw);
913 * @hw: pointer to hardware structure
915 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
928 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
934 ixgbe_raise_eeprom_clk(hw, &eec);
936 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
942 ixgbe_lower_eeprom_clk(hw, &eec);
950 * @hw: pointer to hardware structure
953 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
960 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
961 IXGBE_WRITE_FLUSH(hw);
967 * @hw: pointer to hardware structure
970 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
977 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
978 IXGBE_WRITE_FLUSH(hw);
984 * @hw: pointer to hardware structure
986 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
990 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
995 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
996 IXGBE_WRITE_FLUSH(hw);
1002 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1004 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1009 * @hw: pointer to hardware structure
1011 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1022 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1023 hw_dbg(hw, "EEPROM read failed\n");
1031 hw->eeprom.ops.read(hw, i, &pointer);
1035 hw->eeprom.ops.read(hw, pointer, &length);
1039 hw->eeprom.ops.read(hw, j, &word);
1053 * @hw: pointer to hardware structure
1059 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1071 status = hw->eeprom.ops.read(hw, 0, &checksum);
1074 checksum = ixgbe_calc_eeprom_checksum(hw);
1076 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1089 hw_dbg(hw, "EEPROM read failed\n");
1097 * @hw: pointer to hardware structure
1099 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1109 status = hw->eeprom.ops.read(hw, 0, &checksum);
1112 checksum = ixgbe_calc_eeprom_checksum(hw);
1113 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1116 hw_dbg(hw, "EEPROM read failed\n");
1148 * @hw: pointer to hardware structure
1156 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1160 u32 rar_entries = hw->mac.num_rar_entries;
1163 hw->mac.ops.set_vmdq(hw, index, vmdq);
1180 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1187 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1188 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1190 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1199 * @hw: pointer to hardware structure
1204 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1207 u32 rar_entries = hw->mac.num_rar_entries;
1216 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1219 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1220 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1222 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1227 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1234 * @hw: pointer to hardware structure
1239 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1243 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1245 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1250 * @hw: pointer to hardware structure
1255 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1259 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1261 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1266 * @hw: pointer to hardware structure
1272 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1275 u32 rar_entries = hw->mac.num_rar_entries;
1282 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1285 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1287 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
1290 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1291 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
1293 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1295 hw->addr_ctrl.overflow_promisc = 0;
1297 hw->addr_ctrl.rar_used_count = 1;
1300 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1302 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1303 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1307 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1308 hw->addr_ctrl.mta_in_use = 0;
1309 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1311 hw_dbg(hw, " Clearing MTA\n");
1312 for (i = 0; i < hw->mac.mcft_size; i++)
1313 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1315 if (hw->mac.ops.init_uta_tables)
1316 hw->mac.ops.init_uta_tables(hw);
1323 * @hw: pointer to hardware structure
1328 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1330 u32 rar_entries = hw->mac.num_rar_entries;
1333 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1340 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1341 rar = hw->addr_ctrl.rar_used_count -
1342 hw->addr_ctrl.mc_addr_in_rar_count;
1343 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
1344 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1345 hw->addr_ctrl.rar_used_count++;
1347 hw->addr_ctrl.overflow_promisc++;
1350 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1355 * @hw: pointer to hardware structure
1365 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
1369 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1378 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
1379 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1380 hw->addr_ctrl.overflow_promisc = 0;
1383 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use + 1);
1385 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
1386 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
1391 hw_dbg(hw, " Adding the secondary addresses:\n");
1392 ixgbe_add_uc_addr(hw, ha->addr, 0);
1395 if (hw->addr_ctrl.overflow_promisc) {
1397 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1398 hw_dbg(hw, " Entering address overflow promisc mode\n");
1399 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1401 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1402 hw->addr_ctrl.uc_set_promisc = true;
1406 if ((old_promisc_setting && hw->addr_ctrl.uc_set_promisc) &&
1407 !(hw->addr_ctrl.user_set_promisc)) {
1408 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1409 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1411 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1412 hw->addr_ctrl.uc_set_promisc = false;
1416 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
1422 * @hw: pointer to hardware structure
1432 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1436 switch (hw->mac.mc_filter_type) {
1450 hw_dbg(hw, "MC filter type param set incorrectly\n");
1461 * @hw: pointer to hardware structure
1466 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1473 hw->addr_ctrl.mta_in_use++;
1475 vector = ixgbe_mta_vector(hw, mc_addr);
1476 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1489 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1491 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1496 * @hw: pointer to hardware structure
1504 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1514 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
1515 hw->addr_ctrl.mta_in_use = 0;
1518 hw_dbg(hw, " Clearing MTA\n");
1519 for (i = 0; i < hw->mac.mcft_size; i++)
1520 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1524 hw_dbg(hw, " Adding the multicast addresses:\n");
1525 ixgbe_set_mta(hw, ha->addr);
1529 if (hw->addr_ctrl.mta_in_use > 0)
1530 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1531 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1533 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
1539 * @hw: pointer to hardware structure
1543 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1546 u32 rar_entries = hw->mac.num_rar_entries;
1547 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1552 ixgbe_enable_rar(hw, i);
1555 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1556 hw->mac.mc_filter_type);
1563 * @hw: pointer to hardware structure
1567 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1570 u32 rar_entries = hw->mac.num_rar_entries;
1571 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1576 ixgbe_disable_rar(hw, i);
1579 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1586 * @hw: pointer to hardware structure
1591 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1599 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1604 ret_val = ixgbe_fc_autoneg(hw);
1609 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1612 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1626 switch (hw->fc.current_mode) {
1662 hw_dbg(hw, "Flow control param set incorrectly\n");
1670 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1671 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1673 reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
1676 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1680 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
1683 if (hw->fc.current_mode & ixgbe_fc_tx_pause)
1685 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
1691 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1692 if (hw->fc.send_xon) {
1693 IXGBE_WRITE_REG(hw,
1695 (hw->fc.low_water |
1698 IXGBE_WRITE_REG(hw,
1700 hw->fc.low_water);
1703 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1704 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1709 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
1711 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1713 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1714 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1716 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1724 * @hw: pointer to hardware structure
1729 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1746 hw->mac.ops.check_link(hw, &speed, &link_up, false);
1748 if (hw->fc.disable_fc_autoneg || (!link_up)) {
1749 hw->fc.fc_was_autonegged = false;
1750 hw->fc.current_mode = hw->fc.requested_mode;
1759 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1760 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
1762 hw->fc.fc_was_autonegged = false;
1763 hw->fc.current_mode = hw->fc.requested_mode;
1767 if (hw->mac.type == ixgbe_mac_82599EB) {
1768 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
1770 hw->fc.fc_was_autonegged = false;
1771 hw->fc.current_mode = hw->fc.requested_mode;
1782 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) {
1783 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1786 hw->fc.fc_was_autonegged = false;
1787 hw->fc.current_mode = hw->fc.requested_mode;
1797 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
1798 (hw->phy.media_type == ixgbe_media_type_cx4) ||
1799 ((hw->phy.media_type == ixgbe_media_type_fiber) &&
1801 hw->fc.fc_was_autonegged = false;
1802 hw->fc.current_mode = hw->fc.requested_mode;
1811 (hw->phy.media_type != ixgbe_media_type_backplane)) {
1812 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1813 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1823 if (hw->fc.requested_mode == ixgbe_fc_full) {
1824 hw->fc.current_mode = ixgbe_fc_full;
1825 hw_dbg(hw, "Flow Control = FULL.\n");
1827 hw->fc.current_mode = ixgbe_fc_rx_pause;
1828 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1834 hw->fc.current_mode = ixgbe_fc_tx_pause;
1835 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1840 hw->fc.current_mode = ixgbe_fc_rx_pause;
1841 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1843 hw->fc.current_mode = ixgbe_fc_none;
1844 hw_dbg(hw, "Flow Control = NONE.\n");
1848 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1853 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1854 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
1865 if (hw->fc.requested_mode == ixgbe_fc_full) {
1866 hw->fc.current_mode = ixgbe_fc_full;
1867 hw_dbg(hw, "Flow Control = FULL.\n");
1869 hw->fc.current_mode = ixgbe_fc_rx_pause;
1870 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1876 hw->fc.current_mode = ixgbe_fc_tx_pause;
1877 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1882 hw->fc.current_mode = ixgbe_fc_rx_pause;
1883 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1885 hw->fc.current_mode = ixgbe_fc_none;
1886 hw_dbg(hw, "Flow Control = NONE.\n");
1890 hw->fc.fc_was_autonegged = true;
1898 * @hw: pointer to hardware structure
1902 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
1908 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1909 hw->fc.current_mode = hw->fc.requested_mode;
1916 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1926 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
1927 hw_dbg(hw, "Invalid water mark configuration\n");
1936 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1937 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1947 if (hw->fc.requested_mode == ixgbe_fc_default)
1948 hw->fc.requested_mode = ixgbe_fc_full;
1955 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1970 switch (hw->fc.requested_mode) {
2004 hw_dbg(hw, "Flow control param set incorrectly\n");
2010 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2011 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
2014 if (hw->fc.strict_ieee)
2017 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2018 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
2025 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2037 switch (hw->fc.requested_mode) {
2071 hw_dbg(hw, "Flow control param set incorrectly\n");
2081 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg);
2082 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2090 * @hw: pointer to hardware structure
2097 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2105 number_of_queues = hw->mac.max_rx_queues;
2107 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2110 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2114 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2116 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
2119 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
2132 * @hw: pointer to hardware structure
2138 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2146 if (ixgbe_get_eeprom_semaphore(hw))
2149 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2157 ixgbe_release_eeprom_semaphore(hw);
2163 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
2168 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2170 ixgbe_release_eeprom_semaphore(hw);
2176 * @hw: pointer to hardware structure
2182 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2187 ixgbe_get_eeprom_semaphore(hw);
2189 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2191 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2193 ixgbe_release_eeprom_semaphore(hw);
2198 * @hw: pointer to hardware structure
2203 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2205 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2212 * @hw: pointer to hardware structure
2215 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2219 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2220 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2226 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2231 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2237 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2238 IXGBE_WRITE_FLUSH(hw);
2245 * @hw: pointer to hardware structure
2248 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2250 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2251 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2255 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2260 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2261 IXGBE_WRITE_FLUSH(hw);
2268 * @hw: pointer to hardware structure
2275 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2282 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2289 * @hw: pointer to hardware structure
2297 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2306 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2320 hw->mac.ops.set_lan_id(hw);
2322 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2325 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2337 * @hw: pointer to hardware structure
2342 u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2344 struct ixgbe_adapter *adapter = hw->back;
2358 * @hw: pointer to hardware struct
2362 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2365 u32 rar_entries = hw->mac.num_rar_entries;
2368 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2369 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2376 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2380 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2385 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2388 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2393 hw->mac.ops.clear_rar(hw, rar);
2395 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2404 * @hw: pointer to hardware struct
2408 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2411 u32 rar_entries = hw->mac.num_rar_entries;
2415 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2417 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2419 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2421 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2424 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2431 * @hw: pointer to hardware structure
2433 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2439 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2446 * @hw: pointer to hardware structure
2452 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
2467 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2483 hw_dbg(hw, "No space in VLVF.\n");
2493 * @hw: pointer to hardware structure
2500 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2529 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2551 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2555 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
2562 bits = IXGBE_READ_REG(hw,
2565 IXGBE_WRITE_REG(hw,
2569 bits = IXGBE_READ_REG(hw,
2572 IXGBE_WRITE_REG(hw,
2579 bits = IXGBE_READ_REG(hw,
2582 IXGBE_WRITE_REG(hw,
2585 bits |= IXGBE_READ_REG(hw,
2588 bits = IXGBE_READ_REG(hw,
2591 IXGBE_WRITE_REG(hw,
2594 bits |= IXGBE_READ_REG(hw,
2615 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
2625 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
2629 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
2636 * @hw: pointer to hardware structure
2640 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
2644 for (offset = 0; offset < hw->mac.vft_size; offset++)
2645 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
2648 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
2649 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
2650 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
2658 * @hw: pointer to hardware structure
2665 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2671 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2681 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2701 hw->fc.current_mode = ixgbe_fc_none;
2702 hw->fc.fc_was_autonegged = false;
2711 * @hw: pointer to hardware structure
2718 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2729 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2738 hw->eeprom.ops.read(hw, offset, &caps);
2744 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2747 hw->eeprom.ops.read(hw, offset, wwpn_prefix);