Lines Matching refs:hw
41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
48 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
53 * @hw: pointer to the HW structure
61 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
63 struct ixgbe_adapter *adapter = hw->back;
64 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
93 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
98 * @hw: pointer to hardware structure
103 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
105 struct ixgbe_adapter *adapter = hw->back;
119 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
121 struct ixgbe_mac_info *mac = &hw->mac;
124 ixgbe_identify_phy_generic(hw);
131 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
138 * @hw: pointer to hardware structure
145 static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
147 struct ixgbe_mac_info *mac = &hw->mac;
148 struct ixgbe_phy_info *phy = &hw->phy;
153 phy->ops.identify(hw);
156 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
162 switch (hw->phy.type) {
172 ret_val = phy->ops.identify_sfp(hw);
175 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
181 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
199 * @hw: pointer to hardware structure
204 static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
208 ret_val = ixgbe_start_hw_generic(hw);
212 ixgbe_set_pcie_completion_timeout(hw);
219 * @hw: pointer to hardware structure
225 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
237 if (hw->mac.orig_link_settings_stored)
238 autoc = hw->mac.orig_autoc;
240 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
278 * @hw: pointer to hardware structure
284 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
294 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
309 * @hw: pointer to hardware structure
313 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
318 switch (hw->device_id) {
349 * @hw: pointer to hardware structure
354 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
364 if (hw->fc.requested_mode == ixgbe_fc_pfc)
373 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
375 switch (hw->fc.requested_mode) {
377 hw->fc.requested_mode = ixgbe_fc_tx_pause;
380 hw->fc.requested_mode = ixgbe_fc_none;
389 ret_val = ixgbe_fc_autoneg(hw);
394 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
397 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
413 switch (hw->fc.current_mode) {
449 hw_dbg(hw, "Flow control param set incorrectly\n");
457 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
458 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
461 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
462 if (hw->fc.send_xon) {
463 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
464 (hw->fc.low_water | IXGBE_FCRTL_XONE));
466 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
467 hw->fc.low_water);
470 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
471 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
475 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
477 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
479 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
480 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
482 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
490 * @hw: pointer to hardware structure
495 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
504 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
506 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
516 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
523 hw_dbg(hw, "Autonegotiation did not complete.\n");
536 * @hw: pointer to hardware structure
541 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
546 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
551 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
561 hw_dbg(hw, "Link was indicated but link is down\n");
570 * @hw: pointer to hardware structure
577 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
591 if (hw->phy.type == ixgbe_phy_nl) {
592 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
593 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
594 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
606 hw->phy.ops.read_reg(hw, 0xC79F,
609 hw->phy.ops.read_reg(hw, 0xC00C,
624 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
634 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
648 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&
649 (ixgbe_validate_link_ready(hw) != 0))
654 hw->fc.current_mode = ixgbe_fc_none;
655 hw->fc.fc_was_autonegged = false;
664 * @hw: pointer to hardware structure
671 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
677 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
682 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
697 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
706 status = ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
715 * @hw: pointer to hardware structure
722 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
730 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
734 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
741 * @hw: pointer to hardware structure
747 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
758 hw->mac.ops.stop_adapter(hw);
765 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
768 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
771 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
774 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
777 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
780 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
783 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
786 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
789 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
794 if (hw->phy.reset_disable == false) {
798 phy_status = hw->phy.ops.init(hw);
805 hw->phy.ops.reset(hw);
813 status = ixgbe_disable_pcie_master(hw);
816 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
823 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
824 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
825 IXGBE_WRITE_FLUSH(hw);
830 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
836 hw_dbg(hw, "Reset polling failed to complete.\n");
841 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
843 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
850 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
851 if (hw->mac.orig_link_settings_stored == false) {
852 hw->mac.orig_autoc = autoc;
853 hw->mac.orig_link_settings_stored = true;
854 } else if (autoc != hw->mac.orig_autoc) {
855 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
862 hw->mac.ops.init_rx_addrs(hw);
865 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
876 * @hw: pointer to hardware struct
880 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
884 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
887 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
893 * @hw: pointer to hardware struct
897 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
900 u32 rar_entries = hw->mac.num_rar_entries;
903 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
906 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
909 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
917 * @hw: pointer to hardware structure
924 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
943 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
946 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
951 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
958 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
965 * @hw: pointer to hardware structure
969 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
974 for (offset = 0; offset < hw->mac.vft_size; offset++)
975 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
978 for (offset = 0; offset < hw->mac.vft_size; offset++)
979 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
987 * @hw: pointer to hardware structure
993 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
997 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
999 IXGBE_WRITE_FLUSH(hw);
1001 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1009 * @hw: pointer to hardware structure
1015 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1020 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1021 IXGBE_WRITE_FLUSH(hw);
1030 * @hw: pointer to hardware structure
1036 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1045 if (hw->phy.type == ixgbe_phy_nl) {
1053 hw->phy.ops.write_reg(hw,
1060 hw->phy.ops.read_reg(hw,
1071 hw_dbg(hw, "EEPROM read did not pass.\n");
1077 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1092 * @hw: pointer to hardware structure
1096 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1099 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1104 hw->phy.ops.identify(hw);
1108 if (hw->phy.type == ixgbe_phy_tn ||
1109 hw->phy.type == ixgbe_phy_cu_unknown) {
1110 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1148 if (hw->phy.type == ixgbe_phy_nl) {
1149 hw->phy.ops.identify_sfp(hw);
1151 switch (hw->phy.sfp_type) {
1167 switch (hw->device_id) {