Lines Matching refs:iobase
34 * bank = inb( iobase+BSR);
38 * outb( bank, iobase+BSR);
89 static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
92 static int w83977af_probe(int iobase, int irq, int dma);
97 static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
98 static void w83977af_dma_write(struct w83977af_ir *self, int iobase);
151 * Function w83977af_open (iobase, irq)
156 static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
166 if (!request_region(iobase, CHIP_IO_EXTENT, driver_name)) {
167 IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
168 __func__ , iobase);
172 if (w83977af_probe(iobase, irq, dma) == -1) {
192 self->io.fir_base = iobase;
262 release_region(iobase, CHIP_IO_EXTENT);
274 int iobase;
278 iobase = self->io.fir_base;
313 static int w83977af_probe(int iobase, int irq, int dma)
327 w977_write_reg(0x60, (iobase >> 8) & 0xff, efbase[i]);
328 w977_write_reg(0x61, (iobase) & 0xff, efbase[i]);
348 switch_bank(iobase, SET2);
349 outb(iobase+2, 0x00);
352 switch_bank(iobase, SET0);
353 outb(HCR_EN_IRQ, iobase+HCR);
356 switch_bank(iobase, SET2);
357 outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1);
360 switch_bank(iobase, SET0);
361 outb(HCR_SIR, iobase+HCR);
364 switch_bank(iobase, SET3);
365 version = inb(iobase+AUID);
372 switch_bank(iobase, SET2);
373 outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
376 switch_bank(iobase, SET0);
378 UFR_EN_FIFO,iobase+UFR);
381 switch_bank(iobase, SET4);
382 outb(2048 & 0xff, iobase+6);
383 outb((2048 >> 8) & 0x1f, iobase+7);
397 switch_bank(iobase, SET7);
398 outb(0x40, iobase+7);
415 int iobase;
418 iobase = self->io.fir_base;
424 set = inb(iobase+SSR);
427 switch_bank(iobase, SET0);
428 outb(0, iobase+ICR);
431 switch_bank(iobase, SET2);
432 outb(0x00, iobase+ABHL);
435 case 9600: outb(0x0c, iobase+ABLL); break;
436 case 19200: outb(0x06, iobase+ABLL); break;
437 case 38400: outb(0x03, iobase+ABLL); break;
438 case 57600: outb(0x02, iobase+ABLL); break;
439 case 115200: outb(0x01, iobase+ABLL); break;
459 switch_bank(iobase, SET0);
460 outb(ir_mode, iobase+HCR);
463 switch_bank(iobase, SET2);
464 outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
467 switch_bank(iobase, SET0);
468 outb(0x00, iobase+UFR); /* Reset */
469 outb(UFR_EN_FIFO, iobase+UFR); /* First we must enable FIFO */
470 outb(0xa7, iobase+UFR);
475 switch_bank(iobase, SET0);
477 outb(ICR_EFSFI, iobase+ICR);
480 outb(ICR_ERBRI, iobase+ICR);
483 outb(set, iobase+SSR);
497 int iobase;
503 iobase = self->io.fir_base;
524 set = inb(iobase+SSR);
538 switch_bank(iobase, SET0);
539 outb(ICR_EDMAI, iobase+ICR);
540 w83977af_dma_write(self, iobase);
547 switch_bank(iobase, SET0);
548 outb(ICR_ETXTHI, iobase+ICR);
553 outb(set, iobase+SSR);
559 * Function w83977af_dma_write (self, iobase)
564 static void w83977af_dma_write(struct w83977af_ir *self, int iobase)
574 set = inb(iobase+SSR);
577 switch_bank(iobase, SET0);
578 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
581 switch_bank(iobase, SET2);
582 outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1);
598 switch_bank(iobase, SET0);
600 hcr = inb(iobase+HCR);
601 outb(hcr | HCR_EN_DMA, iobase+HCR);
605 outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR);
609 outb(set, iobase+SSR);
613 * Function w83977af_pio_write (iobase, buf, len, fifo_size)
618 static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
626 set = inb(iobase+SSR);
628 switch_bank(iobase, SET0);
629 if (!(inb_p(iobase+USR) & USR_TSRE)) {
641 outb(buf[actual++], iobase+TBR);
648 outb(set, iobase+SSR);
662 int iobase;
669 iobase = self->io.fir_base;
672 set = inb(iobase+SSR);
675 switch_bank(iobase, SET0);
676 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
679 if (inb(iobase+AUDR) & AUDR_UNDR) {
686 outb(AUDR_UNDR, iobase+AUDR);
701 outb(set, iobase+SSR);
713 int iobase;
723 iobase= self->io.fir_base;
726 set = inb(iobase+SSR);
729 switch_bank(iobase, SET0);
730 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
733 switch_bank(iobase, SET2);
734 outb((inb(iobase+ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL,
735 iobase+ADCR1);
757 switch_bank(iobase, SET0);
758 outb(UFR_RXTL|UFR_TXTL|UFR_RXF_RST|UFR_EN_FIFO, iobase+UFR);
762 switch_bank(iobase, SET0);
764 hcr = inb(iobase+HCR);
765 outb(hcr | HCR_EN_DMA, iobase+HCR);
769 outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR);
772 outb(set, iobase+SSR);
788 int iobase;
796 iobase = self->io.fir_base;
799 set = inb(iobase+SSR);
801 iobase = self->io.fir_base;
804 switch_bank(iobase, SET5);
805 while ((status = inb(iobase+FS_FO)) & FS_FO_FSFDR) {
808 st_fifo->entries[st_fifo->tail].len = inb(iobase+RFLFL);
809 st_fifo->entries[st_fifo->tail].len |= inb(iobase+RFLFH) << 8;
851 switch_bank(iobase, SET0);
852 if (inb(iobase+USR) & USR_RDR) {
861 outb(set, iobase+SSR);
893 outb(set, iobase+SSR);
907 int iobase;
913 iobase = self->io.fir_base;
917 byte = inb(iobase+RBR);
920 } while (inb(iobase+USR) & USR_RDR); /* Data available */
934 int iobase;
938 iobase = self->io.fir_base;
956 set = inb(iobase+SSR);
957 switch_bank(iobase, SET0);
958 outb(AUDR_SFEND, iobase+AUDR);
959 outb(set, iobase+SSR);
1003 int iobase;
1005 iobase = self->io.fir_base;
1006 set = inb(iobase+SSR);
1018 switch_bank(iobase, SET4);
1019 outb(0x01, iobase+TMRL); /* 1 ms */
1020 outb(0x00, iobase+TMRH);
1023 outb(IR_MSL_EN_TMR, iobase+IR_MSL);
1031 switch_bank(iobase, SET4);
1032 outb(0, iobase+IR_MSL);
1035 /* switch_bank(iobase, SET0); */
1036 /* outb(ASCR_CTE, iobase+ASCR); */
1040 w83977af_dma_write(self, iobase);
1067 outb(set, iobase+SSR);
1083 int iobase;
1087 iobase = self->io.fir_base;
1090 set = inb(iobase+SSR);
1091 switch_bank(iobase, SET0);
1093 icr = inb(iobase+ICR);
1094 isr = inb(iobase+ISR) & icr; /* Mask out the interesting ones */
1096 outb(0, iobase+ICR); /* Disable interrupts */
1106 outb(icr, iobase+ICR); /* Restore (new) interrupts */
1107 outb(set, iobase+SSR); /* Restore bank register */
1120 int iobase;
1126 iobase = self->io.fir_base;
1129 set = inb(iobase+SSR);
1130 switch_bank(iobase, SET2);
1131 if ((inb(iobase+RXFDTH) & 0x3f) != 0) {
1135 outb(set, iobase+SSR);
1151 int iobase;
1162 iobase = self->io.fir_base;
1178 set = inb(iobase+SSR);
1181 switch_bank(iobase, SET0);
1183 outb(ICR_EFSFI, iobase+ICR);
1186 outb(ICR_ERBRI, iobase+ICR);
1189 outb(set, iobase+SSR);
1215 int iobase;
1226 iobase = self->io.fir_base;
1239 set = inb(iobase+SSR);
1242 switch_bank(iobase, SET0);
1243 outb(0, iobase+ICR);
1249 outb(set, iobase+SSR);