Lines Matching refs:I_CF_L_0
129 #define I_CF_L_0 0x10
323 #define CRC16(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,7,val) //0 for 32 CRC
326 #define SetFIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,6,val)
327 #define SetMIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,5,val)
328 #define SetSIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,4,val)
330 #define SIRFilter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,3,val)
331 #define Filter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,2,val)
332 #define InvertTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,1,val)
333 #define InvertRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,0,val)
816 tmp = ReadReg(BaseAddr, I_CF_L_0);
817 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
826 tmp = ReadReg(BaseAddr, I_CF_L_0);
827 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
828 WriteRegBit(BaseAddr, I_CF_L_0, 6, val);
836 tmp = ReadReg(BaseAddr, I_CF_L_0);
837 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
838 WriteRegBit(BaseAddr, I_CF_L_0, 5, val);
846 tmp = ReadReg(BaseAddr, I_CF_L_0);
847 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
848 WriteRegBit(BaseAddr, I_CF_L_0, 4, val);