Lines Matching refs:BaseAddr
239 static __u8 ReadReg(unsigned int BaseAddr, int iRegNum)
241 return ((__u8) inb(BaseAddr + iRegNum));
244 static void WriteReg(unsigned int BaseAddr, int iRegNum, unsigned char iVal)
246 outb(iVal, BaseAddr + iRegNum);
249 static int WriteRegBit(unsigned int BaseAddr, unsigned char RegNum,
259 Rtemp = ReadReg(BaseAddr, RegNum);
268 WriteReg(BaseAddr, RegNum, Wtemp);
272 static __u8 CheckRegBit(unsigned int BaseAddr, unsigned char RegNum,
282 temp = ReadReg(BaseAddr, RegNum);
323 #define CRC16(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,7,val) //0 for 32 CRC
325 #define SetVFIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,5,val)
326 #define SetFIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,6,val)
327 #define SetMIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,5,val)
328 #define SetSIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,4,val)
330 #define SIRFilter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,3,val)
331 #define Filter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,2,val)
332 #define InvertTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,1,val)
333 #define InvertRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,0,val)
335 #define EnableTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,4,val)
336 #define EnableRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,3,val)
337 #define EnableDMA(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,2,val)
338 #define SIRRecvAny(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,1,val)
339 #define DiableTrans(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,0,val)
341 #define SetSIRBOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_BOF,val)
342 #define SetSIREOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_EOF,val)
343 #define GetSIRBOF(BaseAddr) ReadReg(BaseAddr,I_SIR_BOF)
344 #define GetSIREOF(BaseAddr) ReadReg(BaseAddr,I_SIR_EOF)
346 #define EnPhys(BaseAddr,val) WriteRegBit(BaseAddr,I_ST_CT_0,7,val)
347 #define IsModeError(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,6) //RO
348 #define IsVFIROn(BaseAddr) CheckRegBit(BaseAddr,0x14,0) //RO for VT1211 only
349 #define IsFIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,5) //RO
350 #define IsMIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,4) //RO
351 #define IsSIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,3) //RO
352 #define IsEnableTX(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,2) //RO
353 #define IsEnableRX(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,1) //RO
354 #define Is16CRC(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,0) //RO
356 #define DisableAdjacentPulseWidth(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,5,val) //1 disable
357 #define DisablePulseWidthAdjust(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,4,val) //1 disable
358 #define UseOneRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,1,val) //0 use two RX
359 #define SlowIRRXLowActive(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,0,val) //0 show RX high=1 in SIR
361 #define EnAllInt(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,7,val)
362 #define TXStart(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,6,val)
363 #define RXStart(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,5,val)
364 #define ClearRXInt(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,4,val) // 1 clear
366 #define IsRXInt(BaseAddr) CheckRegBit(BaseAddr,H_ST,4)
367 #define GetIntIndentify(BaseAddr) ((ReadReg(BaseAddr,H_ST)&0xf1) >>1)
368 #define IsHostBusy(BaseAddr) CheckRegBit(BaseAddr,H_ST,0)
369 #define GetHostStatus(BaseAddr) ReadReg(BaseAddr,H_ST) //RO
371 #define EnTXDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,7,val)
372 #define EnRXDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,6,val)
373 #define SwapDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,5,val)
374 #define EnInternalLoop(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,4,val)
375 #define EnExternalLoop(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,3,val)
377 #define EnTXFIFOHalfLevelInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,4,val) //half empty int (1 half)
378 #define EnTXFIFOUnderrunEOMInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,5,val)
379 #define EnTXFIFOReadyInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,6,val) //int when reach it threshold (setting by bit 4)
381 #define ForceUnderrun(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,7,val) // force an underrun int
382 #define EnTXCRC(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,6,val) //1 for FIR,MIR...0 (not SIR)
383 #define ForceBADCRC(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,5,val) //force an bad CRC
384 #define SendSIP(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,4,val) //send indication pulse for prevent SIR disturb
385 #define ClearEnTX(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,3,val) // opposite to EnTX
387 #define GetTXStatus(BaseAddr) ReadReg(BaseAddr,TX_ST) //RO
389 #define EnRXSpecInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,0,val)
390 #define EnRXFIFOReadyInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,1,val) //enable int when reach it threshold (setting by bit 7)
391 #define EnRXFIFOHalfLevelInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,7,val) //enable int when (1) half full...or (0) just not full
393 #define GetRXStatus(BaseAddr) ReadReg(BaseAddr,RX_ST) //RO
395 #define SetPacketAddr(BaseAddr,addr) WriteReg(BaseAddr,P_ADDR,addr)
397 #define EnGPIOtoRX2(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,7,val)
398 #define EnTimerInt(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,1,val)
399 #define ClearTimerInt(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,0,val)
401 #define WriteGIO(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_L,7,val)
402 #define ReadGIO(BaseAddr) CheckRegBit(BaseAddr,I_T_C_L,7)
403 #define ReadRX(BaseAddr) CheckRegBit(BaseAddr,I_T_C_L,3) //RO
404 #define WriteTX(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_L,0,val)
406 #define EnRX2(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_H,7,val)
407 #define ReadRX2(BaseAddr) CheckRegBit(BaseAddr,I_T_C_H,7)
409 #define GetFIRVersion(BaseAddr) ReadReg(BaseAddr,VERSION)
812 static void SetVFIR(__u16 BaseAddr, __u8 val)
816 tmp = ReadReg(BaseAddr, I_CF_L_0);
817 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
818 WriteRegBit(BaseAddr, I_CF_H_0, 5, val);
821 static void SetFIR(__u16 BaseAddr, __u8 val)
825 WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
826 tmp = ReadReg(BaseAddr, I_CF_L_0);
827 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
828 WriteRegBit(BaseAddr, I_CF_L_0, 6, val);
831 static void SetMIR(__u16 BaseAddr, __u8 val)
835 WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
836 tmp = ReadReg(BaseAddr, I_CF_L_0);
837 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
838 WriteRegBit(BaseAddr, I_CF_L_0, 5, val);
841 static void SetSIR(__u16 BaseAddr, __u8 val)
845 WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
846 tmp = ReadReg(BaseAddr, I_CF_L_0);
847 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
848 WriteRegBit(BaseAddr, I_CF_L_0, 4, val);