Lines Matching refs:iobase
86 int iobase);
95 static int via_ircc_read_dongle_id(int iobase);
101 static void via_ircc_change_dongle_speed(int iobase, int speed,
103 static int RxTimerHandler(struct via_ircc_cb *self, int iobase);
105 static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase);
106 static int upload_rxdata(struct via_ircc_cb *self, int iobase);
314 * Function via_ircc_open (iobase, irq)
356 IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
462 int iobase;
468 iobase = self->io.fir_base;
470 ResetChip(iobase, 5); //hardware reset.
500 int iobase = self->io.fir_base;
504 SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095
506 EnRXFIFOReadyInt(iobase, OFF);
507 EnRXFIFOHalfLevelInt(iobase, OFF);
508 EnTXFIFOHalfLevelInt(iobase, OFF);
509 EnTXFIFOUnderrunEOMInt(iobase, ON);
510 EnTXFIFOReadyInt(iobase, OFF);
511 InvertTX(iobase, OFF);
512 InvertRX(iobase, OFF);
517 EnRXSpecInt(iobase, ON);
521 ResetChip(iobase, 5);
522 EnableDMA(iobase, OFF);
523 EnableTX(iobase, OFF);
524 EnableRX(iobase, OFF);
525 EnRXDMA(iobase, OFF);
526 EnTXDMA(iobase, OFF);
527 RXStart(iobase, OFF);
528 TXStart(iobase, OFF);
529 InitCard(iobase);
530 CommonInit(iobase);
531 SIRFilter(iobase, ON);
532 SetSIR(iobase, ON);
533 CRC16(iobase, ON);
534 EnTXCRC(iobase, 0);
535 WriteReg(iobase, I_ST_CT_0, 0x00);
536 SetBaudRate(iobase, 9600);
537 SetPulseWidth(iobase, 12);
538 SetSendPreambleCount(iobase, 0);
543 via_ircc_change_dongle_speed(iobase, self->io.speed,
546 WriteReg(iobase, I_ST_CT_0, 0x80);
553 static int via_ircc_read_dongle_id(int iobase)
562 * Function via_ircc_change_dongle_speed (iobase, speed, dongle_id)
566 static void via_ircc_change_dongle_speed(int iobase, int speed,
575 __func__, speed, iobase, dongle_id);
583 UseOneRX(iobase, ON); // use one RX pin RX1,RX2
584 InvertTX(iobase, OFF);
585 InvertRX(iobase, OFF);
587 EnRX2(iobase, ON); //sir to rx2
588 EnGPIOtoRX2(iobase, OFF);
590 if (IsSIROn(iobase)) { //sir
592 SlowIRRXLowActive(iobase, ON);
594 SlowIRRXLowActive(iobase, OFF);
596 if (IsMIROn(iobase)) { //mir
598 SlowIRRXLowActive(iobase, OFF);
601 if (IsFIROn(iobase)) { //fir
603 SlowIRRXLowActive(iobase, OFF);
611 UseOneRX(iobase, ON); //use ONE RX....RX1
612 InvertTX(iobase, OFF);
613 InvertRX(iobase, OFF); // invert RX pin
615 EnRX2(iobase, ON);
616 EnGPIOtoRX2(iobase, OFF);
617 if (IsSIROn(iobase)) { //sir
619 SlowIRRXLowActive(iobase, ON);
622 SlowIRRXLowActive(iobase, OFF);
624 if (IsMIROn(iobase)) { //mir
626 SlowIRRXLowActive(iobase, OFF);
629 SlowIRRXLowActive(iobase, ON);
631 if (IsFIROn(iobase)) { //fir
633 SlowIRRXLowActive(iobase, OFF);
635 WriteTX(iobase, ON);
638 SlowIRRXLowActive(iobase, ON);
641 WriteTX(iobase, OFF);
647 UseOneRX(iobase, OFF); // use two RX pin RX1,RX2
648 InvertTX(iobase, OFF);
649 InvertRX(iobase, OFF);
650 SlowIRRXLowActive(iobase, OFF);
651 if (IsSIROn(iobase)) { //sir
652 EnGPIOtoRX2(iobase, OFF);
653 WriteGIO(iobase, OFF);
654 EnRX2(iobase, OFF); //sir to rx2
656 EnGPIOtoRX2(iobase, OFF);
657 WriteGIO(iobase, OFF);
658 EnRX2(iobase, OFF); //fir to rx
666 UseOneRX(iobase, ON); //use ONE RX....RX1
667 InvertTX(iobase, OFF);
668 InvertRX(iobase, ON); // invert RX pin
670 EnRX2(iobase, ON); //sir to rx2
671 EnGPIOtoRX2(iobase, OFF);
673 if( IsSIROn(iobase) ){ //sir
676 SlowIRRXLowActive(iobase, ON);
679 SlowIRRXLowActive(iobase, OFF);
687 if (IsSIROn(iobase))
689 else if (IsMIROn(iobase))
691 else if (IsFIROn(iobase))
693 else if (IsVFIROn(iobase))
695 SI_SetMode(iobase, mode);
713 u16 iobase;
716 iobase = self->io.fir_base;
721 WriteReg(iobase, I_ST_CT_0, 0x0);
732 SetSIR(iobase, ON);
733 CRC16(iobase, ON);
737 SetSIR(iobase, ON);
738 CRC16(iobase, ON);
742 SetMIR(iobase, ON);
746 SetFIR(iobase, ON);
747 SetPulseWidth(iobase, 0);
748 SetSendPreambleCount(iobase, 14);
749 CRC16(iobase, OFF);
750 EnTXCRC(iobase, ON);
754 SetVFIR(iobase, ON);
762 bTmp = (ReadReg(iobase, I_CF_H_1) & 0x03);
764 WriteReg(iobase, I_CF_H_1, bTmp);
767 via_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
770 SetFIFO(iobase, 64);
773 WriteReg(iobase, I_ST_CT_0, 0x80);
775 // EnTXFIFOHalfLevelInt(iobase,ON);
778 //EnAllInt(iobase,ON);
780 if (IsSIROn(iobase)) {
781 SIRFilter(iobase, ON);
782 SIRRecvAny(iobase, ON);
784 SIRFilter(iobase, OFF);
785 SIRRecvAny(iobase, OFF);
810 u16 iobase;
815 iobase = self->io.fir_base;
830 InitCard(iobase);
831 CommonInit(iobase);
832 SIRFilter(iobase, ON);
833 SetSIR(iobase, ON);
834 CRC16(iobase, ON);
835 EnTXCRC(iobase, 0);
836 WriteReg(iobase, I_ST_CT_0, 0x00);
846 SetBaudRate(iobase, self->io.speed);
847 SetPulseWidth(iobase, 12);
848 SetSendPreambleCount(iobase, 0);
849 WriteReg(iobase, I_ST_CT_0, 0x80);
851 EnableTX(iobase, ON);
852 EnableRX(iobase, OFF);
854 ResetChip(iobase, 0);
855 ResetChip(iobase, 1);
856 ResetChip(iobase, 2);
857 ResetChip(iobase, 3);
858 ResetChip(iobase, 4);
860 EnAllInt(iobase, ON);
861 EnTXDMA(iobase, ON);
862 EnRXDMA(iobase, OFF);
867 SetSendByte(iobase, self->tx_buff.len);
868 RXStart(iobase, OFF);
869 TXStart(iobase, ON);
881 u16 iobase;
886 iobase = self->io.fir_base;
916 via_ircc_dma_xmit(self, iobase);
926 static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase)
928 EnTXDMA(iobase, OFF);
930 EnPhys(iobase, ON);
931 EnableTX(iobase, ON);
932 EnableRX(iobase, OFF);
933 ResetChip(iobase, 0);
934 ResetChip(iobase, 1);
935 ResetChip(iobase, 2);
936 ResetChip(iobase, 3);
937 ResetChip(iobase, 4);
938 EnAllInt(iobase, ON);
939 EnTXDMA(iobase, ON);
940 EnRXDMA(iobase, OFF);
950 SetSendByte(iobase, self->tx_fifo.queue[self->tx_fifo.ptr].len);
951 RXStart(iobase, OFF);
952 TXStart(iobase, ON);
966 int iobase;
972 iobase = self->io.fir_base;
977 Tx_status = GetTXStatus(iobase);
985 ResetChip(iobase, 3);
986 ResetChip(iobase, 4);
995 if (IsFIROn(iobase)) {
1009 via_ircc_dma_xmit(self, iobase);
1035 int iobase;
1037 iobase = self->io.fir_base;
1049 EnPhys(iobase, ON);
1050 EnableTX(iobase, OFF);
1051 EnableRX(iobase, ON);
1053 ResetChip(iobase, 0);
1054 ResetChip(iobase, 1);
1055 ResetChip(iobase, 2);
1056 ResetChip(iobase, 3);
1057 ResetChip(iobase, 4);
1059 EnAllInt(iobase, ON);
1060 EnTXDMA(iobase, OFF);
1061 EnRXDMA(iobase, ON);
1064 TXStart(iobase, OFF);
1065 RXStart(iobase, ON);
1078 int iobase)
1085 iobase = self->io.fir_base;
1089 len = GetRecvByte(iobase, self);
1118 len = GetRecvByte(iobase, self);
1123 __func__, len, RxCurCount(iobase, self),
1130 st_fifo->len, len - 4, RxCurCount(iobase, self));
1145 RXStart(iobase,ON);
1146 SetTimer(iobase,4);
1150 EnableRX(iobase, OFF);
1151 EnRXDMA(iobase, OFF);
1152 RXStart(iobase, OFF);
1197 static int upload_rxdata(struct via_ircc_cb *self, int iobase)
1204 len = GetRecvByte(iobase, self);
1234 RXStart(iobase, ON);
1236 EnableRX(iobase, OFF);
1237 EnRXDMA(iobase, OFF);
1238 RXStart(iobase, OFF);
1247 static int RxTimerHandler(struct via_ircc_cb *self, int iobase)
1256 if (CkRxRecv(iobase, self)) {
1259 SetTimer(iobase, 20);
1308 GetHostStatus(iobase), GetRXStatus(iobase));
1314 if ((GetRXStatus(iobase) & 0x10) &&
1315 (RxCurCount(iobase, self) != self->RxLastCount)) {
1316 upload_rxdata(self, iobase);
1322 SetTimer(iobase, 4);
1339 int iobase;
1342 iobase = self->io.fir_base;
1344 iHostIntType = GetHostStatus(iobase);
1355 ClearTimerInt(iobase, 1);
1357 via_ircc_dma_xmit(self, iobase);
1369 RxTimerHandler(self, iobase);
1374 iTxIntType = GetTXStatus(iobase);
1398 iRxIntType = GetRXStatus(iobase);
1413 if (via_ircc_dma_receive_complete(self, iobase)) {
1414 //F01 if(!(IsFIROn(iobase))) via_ircc_dma_receive(self);
1421 RxCurCount(iobase, self),
1425 ResetChip(iobase, 0);
1426 ResetChip(iobase, 1);
1442 int iobase;
1443 iobase = self->io.fir_base;
1447 ResetChip(iobase, 5);
1448 EnableDMA(iobase, OFF);
1449 EnableTX(iobase, OFF);
1450 EnableRX(iobase, OFF);
1451 EnRXDMA(iobase, OFF);
1452 EnTXDMA(iobase, OFF);
1453 RXStart(iobase, OFF);
1454 TXStart(iobase, OFF);
1455 InitCard(iobase);
1456 CommonInit(iobase);
1457 SIRFilter(iobase, ON);
1458 SetSIR(iobase, ON);
1459 CRC16(iobase, ON);
1460 EnTXCRC(iobase, 0);
1461 WriteReg(iobase, I_ST_CT_0, 0x00);
1462 SetBaudRate(iobase, 9600);
1463 SetPulseWidth(iobase, 12);
1464 SetSendPreambleCount(iobase, 0);
1465 WriteReg(iobase, I_ST_CT_0, 0x80);
1482 int iobase;
1486 iobase = self->io.fir_base;
1487 if (CkRxRecv(iobase, self))
1505 int iobase;
1514 iobase = self->io.fir_base;
1542 EnAllInt(iobase, ON);
1543 EnInternalLoop(iobase, OFF);
1544 EnExternalLoop(iobase, OFF);
1556 sprintf(hwname, "VIA @ 0x%x", iobase);
1573 int iobase;
1587 iobase = self->io.fir_base;
1588 EnTXDMA(iobase, OFF);
1589 EnRXDMA(iobase, OFF);
1593 EnAllInt(iobase, OFF);