Lines Matching refs:cfg_base
206 int cfg_base;
232 cfg_base = chip->cfg[cfg];
233 if (!cfg_base)
237 reg = inb(cfg_base);
239 IRDA_DEBUG(2, "%s() no chip at 0x%03x\n", __func__, cfg_base);
244 outb(chip->cid_index, cfg_base);
245 id = inb(cfg_base+1);
256 info.cfg_base = cfg_base;
279 info.cfg_base = cfg_base;
377 info->cfg_base);
400 self->io.cfg_base = info->cfg_base;
551 * Function nsc_ircc_init_108 (iobase, cfg_base, irq, dma)
558 int cfg_base = info->cfg_base;
561 outb(2, cfg_base); /* Mode Control Register (MCTL) */
562 outb(0x00, cfg_base+1); /* Disable device */
565 outb(CFG_108_BAIC, cfg_base);
567 case 0x3e8: outb(0x14, cfg_base+1); break;
568 case 0x2e8: outb(0x15, cfg_base+1); break;
569 case 0x3f8: outb(0x16, cfg_base+1); break;
570 case 0x2f8: outb(0x17, cfg_base+1); break;
585 outb(CFG_108_CSRT, cfg_base);
588 case 0: outb(0x08+temp, cfg_base+1); break;
589 case 1: outb(0x10+temp, cfg_base+1); break;
590 case 3: outb(0x18+temp, cfg_base+1); break;
594 outb(CFG_108_MCTL, cfg_base); /* Mode Control Register (MCTL) */
595 outb(0x03, cfg_base+1); /* Enable device */
608 int cfg_base = info->cfg_base;
612 outb(CFG_108_BAIC, cfg_base);
613 reg = inb(cfg_base+1);
634 outb(CFG_108_CSRT, cfg_base);
635 reg = inb(cfg_base+1);
683 outb(CFG_108_MCTL, cfg_base);
684 reg = inb(cfg_base+1);
715 int cfg_base = info->cfg_base;
720 outb(CFG_338_FER, cfg_base);
721 reg = inb(cfg_base+1);
726 outb(CFG_338_PNP0, cfg_base);
727 reg = inb(cfg_base+1);
732 outb(0x46, cfg_base);
733 reg = (inb(cfg_base+1) & 0xfe) << 2;
735 outb(0x47, cfg_base);
736 reg |= ((inb(cfg_base+1) & 0xfc) << 8);
741 outb(CFG_338_FAR, cfg_base);
742 reg = inb(cfg_base+1);
791 outb(CFG_338_PNP1, cfg_base);
792 reg = inb(cfg_base+1);
797 outb(CFG_338_PNP3, cfg_base);
798 reg = inb(cfg_base+1);
803 outb(CFG_338_PTR, cfg_base);
804 reg = inb(cfg_base+1);
831 int cfg_base = info->cfg_base;
840 outb(CFG_39X_LDN, cfg_base);
841 outb(0x02, cfg_base+1);
846 outb(CFG_39X_ACT, cfg_base);
847 enabled = inb(cfg_base+1) & 0x01;
851 outb(CFG_39X_SIOCF1, cfg_base);
852 outb(0x01, cfg_base+1);
858 outb(CFG_39X_SPC, cfg_base);
859 outb(0x82, cfg_base+1);
873 int cfg_base = info->cfg_base;
878 __func__, cfg_base);
884 outb(CFG_39X_LDN, cfg_base);
885 outb(0x02, cfg_base+1);
888 outb(CFG_39X_BASEH, cfg_base);
889 reg1 = inb(cfg_base+1);
890 outb(CFG_39X_BASEL, cfg_base);
891 reg2 = inb(cfg_base+1);
894 outb(CFG_39X_IRQNUM, cfg_base);
895 irq = inb(cfg_base+1);
896 outb(CFG_39X_IRQSEL, cfg_base);
897 irqt = inb(cfg_base+1);
900 outb(CFG_39X_DMA0, cfg_base);
901 dma1 = inb(cfg_base+1);
902 outb(CFG_39X_DMA1, cfg_base);
903 dma2 = inb(cfg_base+1);
906 outb(CFG_39X_ACT, cfg_base);
907 info->enabled = enabled = inb(cfg_base+1) & 0x01;
909 outb(CFG_39X_SPC, cfg_base);
910 susp = 1 - ((inb(cfg_base+1) & 0x02) >> 1);
917 outb(CFG_39X_ACT, cfg_base);
918 enabled = inb(cfg_base+1) & 0x01;
922 outb(CFG_39X_SIOCF1, cfg_base);
923 outb(0x01, cfg_base+1);
929 outb(CFG_39X_SPC, cfg_base);
930 outb(0x82, cfg_base+1);
947 /* There doesn't seem to be any way of getting the cfg_base.
948 * On my box, cfg_base is in the PnP descriptor of the