Lines Matching refs:iobase
119 static int ali_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
137 static void SIR2FIR(int iobase);
138 static void FIR2SIR(int iobase);
330 IRDA_WARNING("%s(), can't get iobase of 0x%03x\n", __func__,
423 int iobase;
429 iobase = self->io.fir_base;
560 int iobase = info->fir_base;
570 SIR2FIR(iobase);
573 outb(0x40, iobase+FIR_MCR); // benjamin 2000/11/30 11:45AM
576 switch_bank(iobase, BANK3);
577 version = inb(iobase+FIR_ID_VR);
588 switch_bank(iobase, BANK1);
589 outb(RX_FIFO_Threshold, iobase+FIR_FIFO_TR);
592 outb(RX_DMA_Threshold, iobase+FIR_DMA_TR);
595 switch_bank(iobase, BANK2);
596 outb(inb(iobase+FIR_IRDA_CR) | IRDA_CR_CRC, iobase+FIR_IRDA_CR);
601 switch_bank(iobase, BANK0);
603 tmp = inb(iobase+FIR_LCR_B);
607 outb(tmp, iobase+FIR_LCR_B);
610 outb(0x00, iobase+FIR_IER);
614 FIR2SIR(iobase);
620 // outb(UART_IER_RDI, iobase+UART_IER); //benjamin 2000/11/23 01:25PM
703 int iobase, tmp;
707 iobase = self->io.fir_base;
709 switch_bank(iobase, BANK0);
710 self->InterruptID = inb(iobase+FIR_IIR);
711 self->BusStatus = inb(iobase+FIR_BSR);
714 self->LineStatus = inb(iobase+FIR_LSR);
715 //self->ier = inb(iobase+FIR_IER); 2000/12/1 04:32PM
783 switch_bank(iobase, BANK1);
784 tmp = inb(iobase+FIR_CR);
785 outb( tmp& ~CR_TIMER_EN, iobase+FIR_CR);
824 int iobase;
829 iobase = self->io.sir_base;
831 iir = inb(iobase+UART_IIR) & UART_IIR_ID;
834 lsr = inb(iobase+UART_LSR);
836 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n", __func__,
837 iir, lsr, iobase);
878 int iobase;
883 iobase = self->io.sir_base;
891 inb(iobase+UART_RX));
898 } while (inb(iobase+UART_LSR) & UART_LSR_DR);
913 int iobase;
919 iobase = self->io.sir_base;
925 actual = ali_ircc_sir_write(iobase, self->io.fifo_size,
935 while(!(inb(iobase+UART_LSR) & UART_LSR_TEMT))
960 outb(UART_IER_RDI, iobase+UART_IER);
969 int iobase;
978 iobase = self->io.fir_base;
1018 int iobase;
1027 iobase = self->io.fir_base;
1034 SIR2FIR(iobase);
1056 int iobase;
1067 iobase = self->io.sir_base;
1075 FIR2SIR(iobase);
1080 inb(iobase+UART_LSR);
1081 inb(iobase+UART_SCR);
1105 outb(UART_LCR_DLAB | lcr, iobase+UART_LCR); /* Set DLAB */
1106 outb(divisor & 0xff, iobase+UART_DLL); /* Set speed */
1107 outb(divisor >> 8, iobase+UART_DLM);
1108 outb(lcr, iobase+UART_LCR); /* Set 8N1 */
1109 outb(fcr, iobase+UART_FCR); /* Enable FIFO's */
1113 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), iobase+UART_MCR);
1124 int iobase,dongle_id;
1129 iobase = self->io.fir_base; /* or iobase = self->io.sir_base; */
1136 switch_bank(iobase, BANK2);
1137 tmp = inb(iobase+FIR_IRDA_CR);
1153 switch_bank(iobase, BANK2);
1154 outb(tmp, iobase+FIR_IRDA_CR);
1159 outb(tmp, iobase+FIR_IRDA_CR);
1165 outb(tmp, iobase+FIR_IRDA_CR);
1170 outb(tmp, iobase+FIR_IRDA_CR);
1176 outb(tmp, iobase+FIR_IRDA_CR);
1182 outb(tmp, iobase+FIR_IRDA_CR);
1186 outb(tmp & ~0x02, iobase+FIR_IRDA_CR);
1209 switch_bank(iobase, BANK2);
1210 outb(tmp, iobase+FIR_IRDA_CR);
1214 //switch_bank(iobase, BANK2);
1218 outb(tmp, iobase+FIR_IRDA_CR);
1224 outb(tmp, iobase+FIR_IRDA_CR);
1229 outb(tmp, iobase+FIR_IRDA_CR);
1233 outb(tmp & ~0x02, iobase+FIR_IRDA_CR);
1256 switch_bank(iobase, BANK2);
1257 outb(tmp, iobase+FIR_IRDA_CR);
1266 switch_bank(iobase, BANK2);
1267 outb(tmp, iobase+FIR_IRDA_CR);
1291 switch_bank(iobase, BANK2);
1292 outb(tmp, iobase+FIR_IRDA_CR);
1296 switch_bank(iobase, BANK0);
1307 static int ali_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1314 if (!(inb(iobase+UART_LSR) & UART_LSR_THRE)) {
1322 outb(buf[actual], iobase+UART_TX);
1340 int iobase;
1351 iobase = self->io.fir_base;
1375 outb(UART_IER_RDI , iobase+UART_IER);
1404 //int iobase;
1445 int iobase;
1452 iobase = self->io.fir_base;
1530 switch_bank(iobase, BANK1);
1531 outb(TIMER_IIR_500, iobase+FIR_TIMER_IIR);
1535 switch_bank(iobase, BANK1);
1536 outb(TIMER_IIR_1ms, iobase+FIR_TIMER_IIR);
1540 switch_bank(iobase, BANK1);
1541 outb(TIMER_IIR_2ms, iobase+FIR_TIMER_IIR);
1546 outb(inb(iobase+FIR_CR) | CR_TIMER_EN, iobase+FIR_CR);
1576 switch_bank(iobase, BANK0);
1589 int iobase, tmp;
1595 iobase = self->io.fir_base;
1605 switch_bank(iobase, BANK1);
1606 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1617 switch_bank(iobase, BANK0);
1618 outb(LCR_A_FIFO_RESET, iobase+FIR_LCR_A);
1623 switch_bank(iobase, BANK1);
1624 outb(FIFO_OPTI, iobase+FIR_FIFO_TR) ;
1629 switch_bank(iobase, BANK1);
1630 outb(TX_DMA_Threshold, iobase+FIR_DMA_TR);
1635 switch_bank(iobase, BANK2);
1636 outb(Hi, iobase+FIR_TX_DSR_HI);
1637 outb(Lo, iobase+FIR_TX_DSR_LO);
1640 switch_bank(iobase, BANK0);
1641 tmp = inb(iobase+FIR_LCR_B);
1643 outb(((unsigned char)(tmp & 0x3f) | LCR_B_TX_MODE) & ~LCR_B_BW, iobase+FIR_LCR_B);
1644 IRDA_DEBUG(1, "%s(), *** Change to TX mode: FIR_LCR_B = 0x%x ***\n", __func__ , inb(iobase+FIR_LCR_B));
1646 outb(0, iobase+FIR_LSR);
1649 switch_bank(iobase, BANK1);
1650 outb(inb(iobase+FIR_CR) | CR_DMA_EN | CR_DMA_BURST, iobase+FIR_CR);
1652 switch_bank(iobase, BANK0);
1659 int iobase;
1664 iobase = self->io.fir_base;
1667 switch_bank(iobase, BANK1);
1668 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1671 switch_bank(iobase, BANK0);
1672 if((inb(iobase+FIR_LSR) & LSR_FRAME_ABORT) == LSR_FRAME_ABORT)
1716 switch_bank(iobase, BANK0);
1731 int iobase, tmp;
1735 iobase = self->io.fir_base;
1742 switch_bank(iobase, BANK1);
1743 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1746 switch_bank(iobase, BANK0);
1747 outb(0x07, iobase+FIR_LSR);
1751 self->LineStatus = inb(iobase+FIR_LSR) ;
1758 // switch_bank(iobase, BANK0);
1759 outb(LCR_A_FIFO_RESET, iobase+FIR_LCR_A);
1768 //switch_bank(iobase, BANK0);
1769 tmp = inb(iobase+FIR_LCR_B);
1770 outb((unsigned char)(tmp &0x3f) | LCR_B_RX_MODE | LCR_B_BW , iobase + FIR_LCR_B); // 2000/12/1 05:16PM
1771 IRDA_DEBUG(1, "%s(), *** Change To RX mode: FIR_LCR_B = 0x%x ***\n", __func__ , inb(iobase+FIR_LCR_B));
1774 switch_bank(iobase, BANK1);
1775 outb(RX_FIFO_Threshold, iobase+FIR_FIFO_TR);
1776 outb(RX_DMA_Threshold, iobase+FIR_DMA_TR);
1779 // switch_bank(iobase, BANK1);
1780 outb(CR_DMA_EN | CR_DMA_BURST, iobase+FIR_CR);
1782 switch_bank(iobase, BANK0);
1792 int len, i, iobase, val;
1797 iobase = self->io.fir_base;
1799 switch_bank(iobase, BANK0);
1800 MessageCount = inb(iobase+ FIR_LSR)&0x07;
1808 switch_bank(iobase, BANK0);
1809 status = inb(iobase+FIR_LSR);
1811 switch_bank(iobase, BANK2);
1812 len = inb(iobase+FIR_RX_DSR_HI) & 0x0f;
1814 len |= inb(iobase+FIR_RX_DSR_LO);
1883 switch_bank(iobase, BANK0);
1884 val = inb(iobase+FIR_BSR);
1902 switch_bank(iobase, BANK1);
1903 outb(TIMER_IIR_500, iobase+FIR_TIMER_IIR); // 2001/1/2 05:07PM
1906 outb(inb(iobase+FIR_CR) | CR_TIMER_EN, iobase+FIR_CR);
1949 switch_bank(iobase, BANK0);
1968 int iobase;
1978 iobase = self->io.sir_base;
2013 outb(UART_IER_THRI, iobase+UART_IER);
2094 int iobase;
2104 iobase = self->io.fir_base;
2106 switch_bank(iobase, BANK1);
2107 if((inb(iobase+FIR_FIFO_FR) & 0x3f) != 0)
2113 switch_bank(iobase, BANK0);
2166 int iobase = self->io.fir_base; /* or sir_base */
2203 switch_bank(iobase, BANK0);
2204 outb(newMask, iobase+FIR_IER);
2207 outb(newMask, iobase+UART_IER);
2212 static void SIR2FIR(int iobase)
2221 outb(0x28, iobase+UART_MCR);
2222 outb(0x68, iobase+UART_MCR);
2223 outb(0x88, iobase+UART_MCR);
2225 outb(0x60, iobase+FIR_MCR); /* Master Reset */
2226 outb(0x20, iobase+FIR_MCR); /* Master Interrupt Enable */
2228 //tmp = inb(iobase+FIR_LCR_B); /* SIP enable */
2230 //outb(tmp, iobase+FIR_LCR_B);
2235 static void FIR2SIR(int iobase)
2244 outb(0x20, iobase+FIR_MCR); /* IRQ to low */
2245 outb(0x00, iobase+UART_IER);
2247 outb(0xA0, iobase+FIR_MCR); /* Don't set master reset */
2248 outb(0x00, iobase+UART_FCR);
2249 outb(0x07, iobase+UART_FCR);
2251 val = inb(iobase+UART_RX);
2252 val = inb(iobase+UART_LSR);
2253 val = inb(iobase+UART_MSR);