Lines Matching refs:rd32
89 reg = rd32(E1000_MDIC);
94 reg = rd32(E1000_MDICNFG);
159 ctrl_ext = rd32(E1000_CTRL_EXT);
191 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
201 eecd = rd32(E1000_EECD);
249 ctrl_ext = rd32(E1000_CTRL_EXT);
275 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
450 mdic = rd32(E1000_MDIC);
456 mdic = rd32(E1000_MDICNFG);
470 ctrl_ext = rd32(E1000_CTRL_EXT);
680 swfw_sync = rd32(E1000_SW_FW_SYNC);
723 swfw_sync = rd32(E1000_SW_FW_SYNC);
754 if (rd32(E1000_EEMNGCTL) & mask)
763 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
812 reg = rd32(E1000_PCS_CFG0);
817 reg = rd32(E1000_CTRL_EXT);
851 pcs = rd32(E1000_PCS_LSTAT);
898 reg = rd32(E1000_PCS_CFG0);
903 reg = rd32(E1000_CTRL_EXT);
948 ctrl = rd32(E1000_CTRL);
964 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
969 icr = rd32(E1000_ICR);
1040 ctrl = rd32(E1000_CTRL);
1109 ctrl_ext = rd32(E1000_CTRL_EXT);
1113 ctrl_reg = rd32(E1000_CTRL);
1121 reg = rd32(E1000_CONNSW);
1126 reg = rd32(E1000_PCS_LCTL);
1289 rd32(E1000_PRC64);
1290 rd32(E1000_PRC127);
1291 rd32(E1000_PRC255);
1292 rd32(E1000_PRC511);
1293 rd32(E1000_PRC1023);
1294 rd32(E1000_PRC1522);
1295 rd32(E1000_PTC64);
1296 rd32(E1000_PTC127);
1297 rd32(E1000_PTC255);
1298 rd32(E1000_PTC511);
1299 rd32(E1000_PTC1023);
1300 rd32(E1000_PTC1522);
1302 rd32(E1000_ALGNERRC);
1303 rd32(E1000_RXERRC);
1304 rd32(E1000_TNCRS);
1305 rd32(E1000_CEXTERR);
1306 rd32(E1000_TSCTC);
1307 rd32(E1000_TSCTFC);
1309 rd32(E1000_MGTPRC);
1310 rd32(E1000_MGTPDC);
1311 rd32(E1000_MGTPTC);
1313 rd32(E1000_IAC);
1314 rd32(E1000_ICRXOC);
1316 rd32(E1000_ICRXPTC);
1317 rd32(E1000_ICRXATC);
1318 rd32(E1000_ICTXPTC);
1319 rd32(E1000_ICTXATC);
1320 rd32(E1000_ICTXQEC);
1321 rd32(E1000_ICTXQMTC);
1322 rd32(E1000_ICRXDMTC);
1324 rd32(E1000_CBTMPC);
1325 rd32(E1000_HTDPMC);
1326 rd32(E1000_CBRMPC);
1327 rd32(E1000_RPTHC);
1328 rd32(E1000_HGPTC);
1329 rd32(E1000_HTCBDPC);
1330 rd32(E1000_HGORCL);
1331 rd32(E1000_HGORCH);
1332 rd32(E1000_HGOTCL);
1333 rd32(E1000_HGOTCH);
1334 rd32(E1000_LENERRS);
1339 rd32(E1000_SCVPC);
1357 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1362 rxdctl[i] = rd32(E1000_RXDCTL(i));
1371 rx_enabled |= rd32(E1000_RXDCTL(i));
1383 rfctl = rd32(E1000_RFCTL);
1386 rlpml = rd32(E1000_RLPML);
1389 rctl = rd32(E1000_RCTL);
1409 rd32(E1000_ROC);
1410 rd32(E1000_RNBC);
1411 rd32(E1000_MPC);
1426 u32 gcr = rd32(E1000_GCR);
1474 u32 dtxswc = rd32(E1000_DTXSWC);
1493 u32 vt_ctl = rd32(E1000_VT_CTL);
1581 mdicnfg = rd32(E1000_MDICNFG);
1610 ctrl = rd32(E1000_CTRL);
1634 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1656 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1664 icr = rd32(E1000_ICR);