Lines Matching refs:hw
65 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
66 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
76 * @hw: pointer to the HW structure
81 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
86 switch (hw->mac.type) {
103 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
105 struct e1000_phy_info *phy = &hw->phy;
106 struct e1000_nvm_info *nvm = &hw->nvm;
107 struct e1000_mac_info *mac = &hw->mac;
108 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
114 switch (hw->device_id) {
166 hw->phy.media_type = e1000_media_type_internal_serdes;
196 (hw->phy.media_type == e1000_media_type_copper)
238 igb_init_mbx_params_pf(hw);
252 if (igb_sgmii_active_82575(hw)) {
261 igb_reset_mdicnfg_82580(hw);
263 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
266 } else if (hw->mac.type >= e1000_82580) {
275 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
279 ret_val = igb_get_phy_id_82575(hw);
315 * @hw: pointer to the HW structure
320 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
324 if (hw->bus.func == E1000_FUNC_1)
326 else if (hw->bus.func == E1000_FUNC_2)
328 else if (hw->bus.func == E1000_FUNC_3)
331 return igb_acquire_swfw_sync_82575(hw, mask);
336 * @hw: pointer to the HW structure
341 static void igb_release_phy_82575(struct e1000_hw *hw)
345 if (hw->bus.func == E1000_FUNC_1)
347 else if (hw->bus.func == E1000_FUNC_2)
349 else if (hw->bus.func == E1000_FUNC_3)
352 igb_release_swfw_sync_82575(hw, mask);
357 * @hw: pointer to the HW structure
364 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
374 ret_val = hw->phy.ops.acquire(hw);
378 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
380 hw->phy.ops.release(hw);
388 * @hw: pointer to the HW structure
395 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
406 ret_val = hw->phy.ops.acquire(hw);
410 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
412 hw->phy.ops.release(hw);
420 * @hw: pointer to the HW structure
425 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
427 struct e1000_phy_info *phy = &hw->phy;
440 if (!(igb_sgmii_active_82575(hw))) {
442 ret_val = igb_get_phy_id(hw);
446 if (igb_sgmii_uses_mdio_82575(hw)) {
447 switch (hw->mac.type) {
465 ret_val = igb_get_phy_id(hw);
480 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
501 ret_val = igb_get_phy_id(hw);
513 * @hw: pointer to the HW structure
517 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
532 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
536 ret_val = igb_phy_sw_reset(hw);
544 * @hw: pointer to the HW structure
555 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
557 struct e1000_phy_info *phy = &hw->phy;
561 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
567 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
573 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
576 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
582 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
591 ret_val = phy->ops.read_reg(hw,
597 ret_val = phy->ops.write_reg(hw,
602 ret_val = phy->ops.read_reg(hw,
608 ret_val = phy->ops.write_reg(hw,
621 * @hw: pointer to the HW structure
628 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
632 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
636 ret_val = igb_acquire_nvm(hw);
639 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
647 * @hw: pointer to the HW structure
652 static void igb_release_nvm_82575(struct e1000_hw *hw)
654 igb_release_nvm(hw);
655 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
660 * @hw: pointer to the HW structure
666 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
675 if (igb_get_hw_semaphore(hw)) {
688 igb_put_hw_semaphore(hw);
702 igb_put_hw_semaphore(hw);
710 * @hw: pointer to the HW structure
716 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
720 while (igb_get_hw_semaphore(hw) != 0);
727 igb_put_hw_semaphore(hw);
732 * @hw: pointer to the HW structure
740 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
746 if (hw->bus.func == 1)
748 else if (hw->bus.func == E1000_FUNC_2)
750 else if (hw->bus.func == E1000_FUNC_3)
764 (hw->phy.type == e1000_phy_igp_3))
765 igb_phy_init_script_igp3(hw);
772 * @hw: pointer to the HW structure
777 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
782 if (hw->phy.media_type != e1000_media_type_copper) {
783 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
790 hw->mac.get_link_status = !hw->mac.serdes_has_link;
792 ret_val = igb_check_for_copper_link(hw);
800 * @hw: pointer to the HW structure
802 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
807 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
808 !igb_sgmii_active_82575(hw))
828 * @hw: pointer to the HW structure
835 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
838 struct e1000_mac_info *mac = &hw->mac;
883 * @hw: pointer to the HW structure
888 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
892 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
893 igb_sgmii_active_82575(hw))
896 if (!igb_enable_mng_pass_thru(hw)) {
915 * @hw: pointer to the HW structure
920 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
929 ret_val = igb_disable_pcie_master(hw);
934 ret_val = igb_set_pcie_completion_timeout(hw);
953 ret_val = igb_get_auto_rd_done(hw);
965 igb_reset_init_script_82575(hw);
972 ret_val = igb_check_alt_mac_addr(hw);
979 * @hw: pointer to the HW structure
983 static s32 igb_init_hw_82575(struct e1000_hw *hw)
985 struct e1000_mac_info *mac = &hw->mac;
990 ret_val = igb_id_led_init(hw);
998 igb_clear_vfta(hw);
1001 igb_init_rx_addrs(hw, rar_count);
1014 ret_val = igb_setup_link(hw);
1022 igb_clear_hw_cntrs_82575(hw);
1029 * @hw: pointer to the HW structure
1035 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1045 ret_val = igb_setup_serdes_link_82575(hw);
1049 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1053 ret_val = hw->phy.ops.reset(hw);
1059 switch (hw->phy.type) {
1061 ret_val = igb_copper_link_setup_m88(hw);
1064 ret_val = igb_copper_link_setup_igp(hw);
1067 ret_val = igb_copper_link_setup_82580(hw);
1077 ret_val = igb_setup_copper_link(hw);
1084 * @hw: pointer to the HW structure
1091 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1096 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1097 !igb_sgmii_active_82575(hw))
1116 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1129 pcs_autoneg = hw->mac.autoneg;
1186 if (!igb_sgmii_active_82575(hw))
1187 igb_force_mac_fc(hw);
1194 * @hw: pointer to the HW structure
1200 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1202 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1208 * @hw: pointer to the HW structure
1213 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1215 if (hw->mac.type == e1000_82575) {
1218 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1219 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1220 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1221 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1224 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1225 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1228 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1229 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1230 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1231 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1234 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1235 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1236 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1244 * @hw: pointer to the HW structure
1246 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1255 ret_val = igb_check_alt_mac_addr(hw);
1259 ret_val = igb_read_mac_addr(hw);
1267 * @hw: pointer to the HW structure
1272 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1275 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1276 igb_power_down_phy_copper(hw);
1281 * @hw: pointer to the HW structure
1285 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1287 igb_clear_hw_cntrs_base(hw);
1337 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1338 igb_sgmii_active_82575(hw))
1344 * @hw: pointer to the HW structure
1351 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1356 if (hw->mac.type != e1000_82575 ||
1416 * @hw: pointer to the HW structure
1424 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1448 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1455 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1467 * @hw: pointer to the hardware struct
1472 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1486 * @hw: pointer to the hardware struct
1491 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1505 * @hw: pointer to the HW structure
1512 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1517 ret_val = hw->phy.ops.acquire(hw);
1521 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1523 hw->phy.ops.release(hw);
1531 * @hw: pointer to the HW structure
1537 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1542 ret_val = hw->phy.ops.acquire(hw);
1546 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1548 hw->phy.ops.release(hw);
1556 * @hw: pointer to the HW structure
1562 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
1568 if (hw->mac.type != e1000_82580)
1570 if (!igb_sgmii_active_82575(hw))
1573 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1574 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1593 * @hw: pointer to the HW structure
1598 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1604 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1607 hw->dev_spec._82575.global_device_reset = false;
1616 ret_val = igb_disable_pcie_master(hw);
1630 igb_acquire_swfw_sync_82575(hw, swmbsw_mask))
1645 ret_val = igb_get_auto_rd_done(hw);
1657 igb_reset_init_script_82575(hw);
1666 ret_val = igb_reset_mdicnfg_82580(hw);
1671 ret_val = igb_check_alt_mac_addr(hw);
1675 igb_release_swfw_sync_82575(hw, swmbsw_mask);