Lines Matching defs:bc
263 #define tenms_to_flags(bc,tenms) ((tenms * bc->bitrate) / 800)
267 static inline void baycom_int_freq(struct baycom_state *bc)
274 bc->debug_vals.cur_intcnt++;
275 if (time_after_eq(cur_jiffies, bc->debug_vals.last_jiffies + HZ)) {
276 bc->debug_vals.last_jiffies = cur_jiffies;
277 bc->debug_vals.last_intcnt = bc->debug_vals.cur_intcnt;
278 bc->debug_vals.cur_intcnt = 0;
279 bc->debug_vals.last_pllcorr = bc->debug_vals.cur_pllcorr;
280 bc->debug_vals.cur_pllcorr = 0;
295 static int eppconfig(struct baycom_state *bc)
304 bc->cfg.intclk ? "int" : "ext",
305 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
306 (bc->cfg.fclk + 8 * bc->cfg.bps) / (16 * bc->cfg.bps),
307 bc->cfg.loopback ? ",loopback" : "");
308 sprintf(portarg, "%ld", bc->pdev->port->base);
316 static inline void do_kiss_params(struct baycom_state *bc,
330 bc->ch_params.tx_delay = data[1];
331 PKP("TX delay = %ums", 10 * bc->ch_params.tx_delay);
334 bc->ch_params.ppersist = data[1];
335 PKP("p persistence = %u", bc->ch_params.ppersist);
338 bc->ch_params.slottime = data[1];
339 PKP("slot time = %ums", bc->ch_params.slottime);
342 bc->ch_params.tx_tail = data[1];
343 PKP("TX tail = %ums", bc->ch_params.tx_tail);
346 bc->ch_params.fulldup = !!data[1];
347 PKP("%s duplex", bc->ch_params.fulldup ? "full" : "half");
357 static void encode_hdlc(struct baycom_state *bc)
366 if (bc->hdlctx.bufcnt > 0)
368 skb = bc->skb;
371 bc->skb = NULL;
373 wp = bc->hdlctx.buf;
411 bc->hdlctx.bufptr = bc->hdlctx.buf;
412 bc->hdlctx.bufcnt = wp - bc->hdlctx.buf;
414 bc->dev->stats.tx_packets++;
419 static int transmit(struct baycom_state *bc, int cnt, unsigned char stat)
421 struct parport *pp = bc->pdev->port;
425 if (bc->hdlctx.state == tx_tail && !(stat & EPP_PTTBIT))
426 bc->hdlctx.state = tx_idle;
427 if (bc->hdlctx.state == tx_idle && bc->hdlctx.calibrate <= 0) {
428 if (bc->hdlctx.bufcnt <= 0)
429 encode_hdlc(bc);
430 if (bc->hdlctx.bufcnt <= 0)
432 if (!bc->ch_params.fulldup) {
434 bc->hdlctx.slotcnt = bc->ch_params.slottime;
437 if ((--bc->hdlctx.slotcnt) > 0)
439 bc->hdlctx.slotcnt = bc->ch_params.slottime;
440 if ((random32() % 256) > bc->ch_params.ppersist)
444 if (bc->hdlctx.state == tx_idle && bc->hdlctx.bufcnt > 0) {
445 bc->hdlctx.state = tx_keyup;
446 bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_delay);
447 bc->ptt_keyed++;
450 switch (bc->hdlctx.state) {
452 i = min_t(int, cnt, bc->hdlctx.flags);
454 bc->hdlctx.flags -= i;
455 if (bc->hdlctx.flags <= 0)
456 bc->hdlctx.state = tx_data;
467 if (bc->hdlctx.bufcnt <= 0) {
468 encode_hdlc(bc);
469 if (bc->hdlctx.bufcnt <= 0) {
470 bc->hdlctx.state = tx_tail;
471 bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_tail);
475 i = min_t(int, cnt, bc->hdlctx.bufcnt);
476 bc->hdlctx.bufcnt -= i;
478 if (i != pp->ops->epp_write_data(pp, bc->hdlctx.bufptr, i, 0))
480 bc->hdlctx.bufptr += i;
484 encode_hdlc(bc);
485 if (bc->hdlctx.bufcnt > 0) {
486 bc->hdlctx.state = tx_data;
489 i = min_t(int, cnt, bc->hdlctx.flags);
492 bc->hdlctx.flags -= i;
504 if (bc->hdlctx.calibrate <= 0)
506 i = min_t(int, cnt, bc->hdlctx.calibrate);
508 bc->hdlctx.calibrate -= i;
526 struct baycom_state *bc = netdev_priv(dev);
531 if (bc->hdlcrx.bufcnt < 4)
533 if (!check_crc_ccitt(bc->hdlcrx.buf, bc->hdlcrx.bufcnt))
535 pktlen = bc->hdlcrx.bufcnt-2+1; /* KISS kludge */
543 memcpy(cp, bc->hdlcrx.buf, pktlen - 1);
551 struct baycom_state *bc = netdev_priv(dev);
552 struct parport *pp = bc->pdev->port;
559 numbits = bc->hdlcrx.numbits;
560 state = bc->hdlcrx.state;
561 bitstream = bc->hdlcrx.bitstream;
562 bitbuf = bc->hdlcrx.bitbuf;
591 bc->hdlcrx.bufcnt = 0;
592 bc->hdlcrx.bufptr = bc->hdlcrx.buf;
605 if (bc->hdlcrx.bufcnt >= TXBUFFER_SIZE) {
608 *(bc->hdlcrx.bufptr)++ = bitbuf >> (16-numbits);
609 bc->hdlcrx.bufcnt++;
615 bc->hdlcrx.numbits = numbits;
616 bc->hdlcrx.state = state;
617 bc->hdlcrx.bitstream = bitstream;
618 bc->hdlcrx.bitbuf = bitbuf;
638 struct baycom_state *bc;
645 bc = container_of(work, struct baycom_state, run_work.work);
646 dev = bc->dev;
647 if (!bc->work_running)
649 baycom_int_freq(bc);
650 pp = bc->pdev->port;
654 bc->stat = stat;
655 bc->debug_vals.last_pllcorr = stat;
657 if (bc->modem == EPP_FPGAEXTSTATUS) {
678 if (transmit(bc, cnt2, stat))
685 bc->stat = stat;
705 if (transmit(bc, cnt, stat))
729 if (bc->bitrate < 50000)
731 else if (bc->bitrate < 100000)
743 bc->debug_vals.mod_cycles = time2 - time1;
744 bc->debug_vals.demod_cycles = time3 - time2;
746 schedule_delayed_work(&bc->run_work, 1);
747 if (!bc->skb)
761 struct baycom_state *bc = netdev_priv(dev);
764 do_kiss_params(bc, skb->data, skb->len);
768 if (bc->skb)
776 bc->skb = skb;
796 struct baycom_state *bc = netdev_priv(dev);
799 if (!parport_claim(bc->pdev))
816 struct baycom_state *bc = netdev_priv(dev);
833 memset(&bc->modem, 0, sizeof(bc->modem));
834 bc->pdev = parport_register_device(pp, dev->name, NULL, epp_wakeup,
837 if (!bc->pdev) {
841 if (parport_claim(bc->pdev)) {
843 parport_unregister_device(bc->pdev);
847 INIT_DELAYED_WORK(&bc->run_work, epp_bh);
848 bc->work_running = 1;
849 bc->modem = EPP_CONVENTIONAL;
850 if (eppconfig(bc))
853 bc->modem = /*EPP_FPGA*/ EPP_FPGAEXTSTATUS;
886 bc->bitrate = i * (8 * HZ) / tstart;
888 i = bc->bitrate >> 3;
894 bc_drvname, bc->bitrate, j, bc->bitrate >> (j+2));
901 bc->hdlcrx.state = 0;
902 bc->hdlcrx.numbits = 0;
903 bc->hdlctx.state = tx_idle;
904 bc->hdlctx.bufcnt = 0;
905 bc->hdlctx.slotcnt = bc->ch_params.slottime;
906 bc->hdlctx.calibrate = 0;
908 schedule_delayed_work(&bc->run_work, 1);
915 parport_release(bc->pdev);
916 parport_unregister_device(bc->pdev);
924 struct baycom_state *bc = netdev_priv(dev);
925 struct parport *pp = bc->pdev->port;
928 bc->work_running = 0;
929 cancel_delayed_work_sync(&bc->run_work);
930 bc->stat = EPP_DCDBIT;
934 parport_release(bc->pdev);
935 parport_unregister_device(bc->pdev);
936 if (bc->skb)
937 dev_kfree_skb(bc->skb);
938 bc->skb = NULL;
946 static int baycom_setmode(struct baycom_state *bc, const char *modestr)
951 bc->cfg.intclk = 1;
953 bc->cfg.intclk = 0;
955 bc->cfg.extmodem = 0;
957 bc->cfg.extmodem = 1;
959 bc->cfg.loopback = 0;
961 bc->cfg.loopback = 1;
963 bc->cfg.fclk = simple_strtoul(cp+5, NULL, 0);
964 if (bc->cfg.fclk < 1000000)
965 bc->cfg.fclk = 1000000;
966 if (bc->cfg.fclk > 25000000)
967 bc->cfg.fclk = 25000000;
970 bc->cfg.bps = simple_strtoul(cp+4, NULL, 0);
971 if (bc->cfg.bps < 1000)
972 bc->cfg.bps = 1000;
973 if (bc->cfg.bps > 1500000)
974 bc->cfg.bps = 1500000;
983 struct baycom_state *bc = netdev_priv(dev);
996 hi.data.cp.tx_delay = bc->ch_params.tx_delay;
997 hi.data.cp.tx_tail = bc->ch_params.tx_tail;
998 hi.data.cp.slottime = bc->ch_params.slottime;
999 hi.data.cp.ppersist = bc->ch_params.ppersist;
1000 hi.data.cp.fulldup = bc->ch_params.fulldup;
1006 bc->ch_params.tx_delay = hi.data.cp.tx_delay;
1007 bc->ch_params.tx_tail = hi.data.cp.tx_tail;
1008 bc->ch_params.slottime = hi.data.cp.slottime;
1009 bc->ch_params.ppersist = hi.data.cp.ppersist;
1010 bc->ch_params.fulldup = hi.data.cp.fulldup;
1011 bc->hdlctx.slotcnt = 1;
1033 hi.data.cs.ptt = !!(bc->stat & EPP_PTTBIT);
1034 hi.data.cs.dcd = !(bc->stat & EPP_DCDBIT);
1035 hi.data.cs.ptt_keyed = bc->ptt_keyed;
1043 hi.data.ocs.ptt = !!(bc->stat & EPP_PTTBIT);
1044 hi.data.ocs.dcd = !(bc->stat & EPP_DCDBIT);
1045 hi.data.ocs.ptt_keyed = bc->ptt_keyed;
1051 bc->hdlctx.calibrate = hi.data.calibrate * bc->bitrate / 8;
1060 bc->cfg.intclk ? "int" : "ext",
1061 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
1062 bc->cfg.loopback ? ",loopback" : "");
1069 return baycom_setmode(bc, hi.data.modename);
1107 struct baycom_state *bc;
1112 bc = netdev_priv(dev);
1116 bc->ch_params = dflt_ch_params;
1117 bc->ptt_keyed = 0;
1124 bc->skb = NULL;
1162 struct baycom_state *bc = netdev_priv(dev);
1167 bc->dev = dev;
1168 bc->magic = BAYCOM_MAGIC;
1169 bc->cfg.fclk = 19666600;
1170 bc->cfg.bps = 9600;
1227 struct baycom_state *bc = netdev_priv(dev);
1228 if (bc->magic == BAYCOM_MAGIC) {