Lines Matching refs:txreg
3139 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3270 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3274 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3276 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3278 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3283 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3285 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3287 writel(txreg, base + NvRegTxDeferral);
3290 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3293 txreg = NVREG_TX_WM_DESC2_3_1000;
3295 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3297 writel(txreg, base + NvRegTxWatermark);
5403 u32 powerstate, txreg;
5573 txreg = readl(base + NvRegTransmitPoll);
5582 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5606 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);