Lines Matching refs:MII_READ
1114 #define MII_READ (-1)
1134 if (value != MII_READ) {
1145 } else if (value != MII_READ) {
1180 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1195 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1247 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1257 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1272 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1283 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1294 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1297 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1312 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1336 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1343 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1351 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1367 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1372 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1387 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1394 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1407 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1412 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1463 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1475 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1494 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3146 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3147 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3187 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3188 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3194 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3195 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3267 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
4126 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4136 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4214 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4231 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4240 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4258 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4281 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4286 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4360 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4570 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4580 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4696 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4697 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5160 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5356 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5741 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5746 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5764 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5779 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5853 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5860 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);