Lines Matching defs:phyaddr
754 int phyaddr;
1170 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1180 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1195 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1197 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1205 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1209 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1213 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1217 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1221 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1225 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1229 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1247 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1249 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1253 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1257 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1260 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1265 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1272 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1274 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1283 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1285 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1294 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1297 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1304 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1312 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1320 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1336 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1339 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1343 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1345 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1351 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1353 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1359 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1363 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1367 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1368 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1372 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1375 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1379 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1383 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1387 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1390 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1394 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1395 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1399 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1403 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1407 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1408 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1412 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1415 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1419 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1423 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1432 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1436 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1440 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1444 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1448 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1452 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1456 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1463 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1465 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1471 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1475 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1478 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1482 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1491 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1494 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1499 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
3146 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3147 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3187 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3188 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3194 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3195 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3267 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
4126 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4136 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4148 ecmd->phy_address = np->phyaddr;
4164 if (ecmd->phy_address != np->phyaddr) {
4214 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4228 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4231 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4235 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4240 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4251 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4258 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4277 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4281 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4283 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4286 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4299 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4360 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4370 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4570 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4576 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4580 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4582 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4696 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4697 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5159 mii_rw(dev, np->phyaddr, MII_BMCR,
5160 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5244 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5355 mii_rw(dev, np->phyaddr, MII_BMCR,
5356 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5738 int phyaddr = i & 0x1F;
5741 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5746 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5755 pci_name(pci_dev), id1, id2, phyaddr);
5756 np->phyaddr = phyaddr;
5764 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5779 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5801 np->phyaddr,
5852 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5853 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5856 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5857 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5860 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5862 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);