Lines Matching defs:phy_reserved
1191 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1272 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1273 phy_reserved |= PHY_REALTEK_INIT7;
1274 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1336 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1337 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1338 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1339 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1343 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1344 phy_reserved |= PHY_CICADA_INIT5;
1345 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1351 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1352 phy_reserved |= PHY_CICADA_INIT6;
1353 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1367 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1368 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1372 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1373 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1374 phy_reserved |= PHY_VITESSE_INIT3;
1375 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1387 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1388 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1389 phy_reserved |= PHY_VITESSE_INIT3;
1390 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1394 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1395 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1407 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1408 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1412 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1413 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1414 phy_reserved |= PHY_VITESSE_INIT8;
1415 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1463 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1464 phy_reserved |= PHY_REALTEK_INIT7;
1465 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1475 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1476 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1477 phy_reserved |= PHY_REALTEK_INIT3;
1478 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
5847 u16 phy_reserved, mii_control;
5853 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5854 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5855 phy_reserved |= PHY_REALTEK_INIT8;
5856 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);