Lines Matching refs:reg_data
837 u32 reg_data;
865 reg_data = er32(TXDCTL(0));
866 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
868 ew32(TXDCTL(0), reg_data);
871 reg_data = er32(TXDCTL(1));
872 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
874 ew32(TXDCTL(1), reg_data);
877 reg_data = er32(TCTL);
878 reg_data |= E1000_TCTL_RTLC;
879 ew32(TCTL, reg_data);
882 reg_data = er32(TCTL_EXT);
883 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
884 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
885 ew32(TCTL_EXT, reg_data);
888 reg_data = er32(TIPG);
889 reg_data &= ~E1000_TIPG_IPGT_MASK;
890 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
891 ew32(TIPG, reg_data);
893 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
894 reg_data &= ~0x00100000;
895 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
1113 u16 reg_data;
1130 ®_data);
1133 reg_data |= 0x3F;
1135 reg_data);
1140 ®_data);
1143 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1146 reg_data);
1201 u16 reg_data, reg_data2;
1203 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1206 reg_data);
1217 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1225 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1228 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1230 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1232 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1247 u16 reg_data, reg_data2;
1251 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1254 reg_data);
1265 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1273 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1275 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1276 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);