Lines Matching refs:t3_write_reg
57 t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |
102 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
139 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
167 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
171 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
177 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
178 t3_write_reg(adap, A_TP_PIO_DATA, 0xc0000011);
189 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0);
199 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
205 t3_write_reg(adap, A_XGM_RX_CFG + oft,
210 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
211 t3_write_reg(adap, A_TP_PIO_DATA, store);
238 t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1 + oft, addr_lo);
239 t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_HIGH_1 + oft, addr_hi);
270 t3_write_reg(mac->adapter, reg, v);
281 t3_write_reg(mac->adapter, reg, v);
309 t3_write_reg(adap, A_XGM_RX_CFG + oft, val);
332 t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo);
333 t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi);
362 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
377 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
384 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
404 t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);
420 t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
423 t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
460 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
475 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
476 t3_write_reg(adap, A_TP_PIO_DATA,
479 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
483 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
485 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
502 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
511 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
520 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
527 t3_write_reg(mac->adapter, A_XGM_RESET_CTRL + mac->offset, val);
548 t3_write_reg(adap, A_TP_PIO_ADDR,
579 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
581 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen);
651 t3_write_reg(mac->adapter, A_TP_MIB_INDEX, mac->offset ? 51 : 50);