Lines Matching refs:t3_write_reg
86 t3_write_reg(adapter, p->reg_addr + offset, p->val);
106 t3_write_reg(adapter, addr, v | val);
127 t3_write_reg(adap, addr_reg, start_idx);
164 t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start);
165 t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);
199 t3_write_reg(adap, A_MI1_CFG, val);
217 t3_write_reg(adapter, A_MI1_ADDR, addr);
218 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
236 t3_write_reg(adapter, A_MI1_ADDR, addr);
237 t3_write_reg(adapter, A_MI1_DATA, val);
238 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
260 t3_write_reg(adapter, A_MI1_ADDR, addr);
261 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
262 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
280 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3));
300 t3_write_reg(adapter, A_MI1_DATA, val);
301 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
773 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
798 t3_write_reg(adapter, A_SF_DATA, val);
799 t3_write_reg(adapter, A_SF_OP,
927 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
1153 t3_write_reg(adap, A_CIM_HOST_ACC_CTRL, CIM_CTL_BASE + addr);
1175 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, 0);
1178 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, 0);
1191 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, rx_hash_high);
1192 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, rx_hash_low);
1220 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0);
1244 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1273 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, 0);
1275 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0);
1303 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1418 t3_write_reg(adapter, reg, status);
1799 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause);
1846 t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause);
1879 t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause);
1933 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause);
1977 t3_write_reg(adapter, A_TP_INT_ENABLE,
1981 t3_write_reg(adapter, A_CPL_INTR_ENABLE,
1983 t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
1987 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK);
1988 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
1991 t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter));
1994 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
1996 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK);
1997 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask);
2010 t3_write_reg(adapter, A_PL_INT_ENABLE0, 0);
2048 t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff);
2051 t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff);
2052 t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff);
2060 t3_write_reg(adapter, A_XGM_XGM_INT_ENABLE + pi->mac.offset,
2068 t3_write_reg(adapter, A_XGM_XGM_INT_DISABLE + pi->mac.offset,
2084 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), XGM_INTR_MASK);
2101 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), 0);
2118 t3_write_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx), 0xffffffff);
2144 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
2145 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
2146 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0x17ffffff);
2147 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
2149 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
2150 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
2151 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff);
2152 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
2154 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2174 t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0);
2175 t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0);
2176 t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0);
2177 t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0);
2178 t3_write_reg(adap, A_SG_CONTEXT_MASK0, 0xffffffff);
2179 t3_write_reg(adap, A_SG_CONTEXT_MASK1, 0xffffffff);
2180 t3_write_reg(adap, A_SG_CONTEXT_MASK2, 0xffffffff);
2181 t3_write_reg(adap, A_SG_CONTEXT_MASK3, 0xffffffff);
2182 t3_write_reg(adap, A_SG_CONTEXT_CMD,
2218 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) |
2220 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) |
2223 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, base_addr);
2225 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
2259 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, base_addr);
2261 t3_write_reg(adapter, A_SG_CONTEXT_DATA1,
2264 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) |
2267 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
2300 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) |
2302 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr);
2306 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2308 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres);
2337 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size));
2338 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr);
2340 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2344 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) |
2363 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2364 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2365 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2366 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID);
2367 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable));
2368 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2387 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2388 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2389 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE));
2390 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2391 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0);
2392 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2411 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2412 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2413 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2414 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2415 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2416 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2435 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2436 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2437 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2438 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2439 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2440 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2464 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16);
2465 t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) |
2475 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2502 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2604 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val);
2609 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2615 t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config);
2633 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE,
2644 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2686 t3_write_reg((adap), A_ ## reg, (start)); \
2715 t3_write_reg(adap, A_TP_PMM_SIZE,
2718 t3_write_reg(adap, A_TP_PMM_TX_BASE, 0);
2719 t3_write_reg(adap, A_TP_PMM_TX_PAGE_SIZE, p->tx_pg_size);
2720 t3_write_reg(adap, A_TP_PMM_TX_MAX_PAGE, p->tx_num_pgs);
2724 t3_write_reg(adap, A_TP_PMM_RX_BASE, 0);
2725 t3_write_reg(adap, A_TP_PMM_RX_PAGE_SIZE, p->rx_pg_size);
2726 t3_write_reg(adap, A_TP_PMM_RX_MAX_PAGE, p->rx_num_pgs);
2732 t3_write_reg(adap, A_TP_CMM_MM_MAX_PSTRUCT, pstructs);
2737 t3_write_reg(adap, A_TP_CMM_TIMER_BASE, V_CMTIMERMAXNUM(timers) | m);
2745 t3_write_reg(adap, A_CIM_SDRAM_BASE_ADDR, m);
2746 t3_write_reg(adap, A_CIM_SDRAM_ADDR_SIZE, p->cm_size - m);
2758 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2759 t3_write_reg(adap, A_TP_PIO_DATA, val);
2764 t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
2767 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2770 t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
2776 t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
2777 t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
2789 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
2790 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
2806 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
2807 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
2808 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
2809 t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
2834 t3_write_reg(adap, A_TP_TIMER_RESOLUTION, V_TIMERRESOLUTION(tre) |
2837 t3_write_reg(adap, A_TP_DACK_TIMER,
2839 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG0, 0x3020100);
2840 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG1, 0x7060504);
2841 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG2, 0xb0a0908);
2842 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG3, 0xf0e0d0c);
2843 t3_write_reg(adap, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) |
2850 t3_write_reg(adap, A_TP_MSL, adap->params.rev > 0 ? 0 : 2 SECONDS);
2851 t3_write_reg(adap, A_TP_RXT_MIN, tps / (1000 / TP_RTO_MIN));
2852 t3_write_reg(adap, A_TP_RXT_MAX, 64 SECONDS);
2853 t3_write_reg(adap, A_TP_PERS_MIN, 5 SECONDS);
2854 t3_write_reg(adap, A_TP_PERS_MAX, 64 SECONDS);
2855 t3_write_reg(adap, A_TP_KEEP_IDLE, 7200 SECONDS);
2856 t3_write_reg(adap, A_TP_KEEP_INTVL, 75 SECONDS);
2857 t3_write_reg(adap, A_TP_INIT_SRTT, 3 SECONDS);
2858 t3_write_reg(adap, A_TP_FINWAIT2_TIMER, 600 SECONDS);
2886 t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) |
2889 t3_write_reg(adap, A_TP_PARA_REG3, val);
2903 t3_write_reg(adap, A_TP_PARA_REG7,
3005 t3_write_reg(adap, A_TP_MTU_TABLE,
3014 t3_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
3034 t3_write_reg(adap, A_TP_MTU_TABLE, 0xff000000 | i);
3055 t3_write_reg(adap, A_TP_CCTRL_TABLE,
3076 t3_write_reg((adap), A_ULPRX_ ## name ## _LLIMIT, (start)); \
3077 t3_write_reg((adap), A_ULPRX_ ## name ## _ULIMIT, \
3082 t3_write_reg((adap), A_ULPTX_ ## name ## _LLIMIT, (start)); \
3083 t3_write_reg((adap), A_ULPTX_ ## name ## _ULIMIT, \
3097 t3_write_reg(adap, A_ULPRX_TDDP_TAGMASK, 0xffffffff);
3113 t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, be32_to_cpu(*buf++));
3114 t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, be32_to_cpu(*buf++));
3115 t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, be32_to_cpu(*buf++));
3116 t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, be32_to_cpu(*buf++));
3117 t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, be32_to_cpu(*buf++));
3119 t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);
3123 t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, 0);
3194 t3_write_reg(adap, A_TP_TM_PIO_ADDR,
3201 t3_write_reg(adap, A_TP_TM_PIO_DATA, v);
3214 t3_write_reg(adap, A_TP_RESET, F_FLSTINITENABLE);
3222 t3_write_reg(adap, A_TP_RESET, F_TPRESET);
3246 t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_ENFORCEPKT |
3249 t3_write_reg(adap, A_PM1_TX_CFG,
3254 t3_write_reg(adap, A_ULPTX_DMA_WEIGHT,
3256 t3_write_reg(adap, A_MPS_CFG, F_TPTXPORT0EN | F_TPTXPORT1EN |
3259 t3_write_reg(adap, A_PM1_TX_CFG, 0x80008000);
3261 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
3264 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE,
3275 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0);
3280 t3_write_reg(adapter, A_XGM_XAUI_IMP,
3288 t3_write_reg(adapter, A_XGM_RGMII_IMP,
3299 t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET |
3328 t3_write_reg(adapter, addr, val);
3362 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
3367 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
3378 t3_write_reg(adapter, mc7->offset + A_MC7_PARM,
3384 t3_write_reg(adapter, mc7->offset + A_MC7_CFG,
3401 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100);
3419 t3_write_reg(adapter, mc7->offset + A_MC7_REF,
3423 t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN);
3424 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0);
3425 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);
3426 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,
3428 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));
3507 t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);
3567 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
3568 t3_write_reg(adapter, A_PM1_RX_MODE, 0);
3569 t3_write_reg(adapter, A_PM1_TX_MODE, 0);
3573 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter));
3575 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3576 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3702 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset,
3714 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */
3716 t3_write_reg(adapter, A_T3DBG_GPIO_EN,
3718 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0);
3719 t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff));
3725 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3729 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3731 t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val);
3748 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE);
3781 t3_write_reg(adap, A_CIM_IBQ_DBG_DATA, 0);
3784 t3_write_reg(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGEN |