Lines Matching refs:t3_read_reg
57 u32 val = t3_read_reg(adapter, reg);
104 u32 v = t3_read_reg(adapter, addr) & ~mask;
107 t3_read_reg(adapter, addr); /* flush */
128 *vals++ = t3_read_reg(adap, data_reg);
166 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
168 val = t3_read_reg(adap,
173 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
175 val64 = t3_read_reg(adap,
221 ret = t3_read_reg(adapter, A_MI1_DATA);
284 ret = t3_read_reg(adapter, A_MI1_DATA);
771 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
776 *valp = t3_read_reg(adapter, A_SF_DATA);
796 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
933 *vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
1149 if (t3_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
1157 *valp++ = t3_read_reg(adap, A_CIM_HOST_ACC_DATA);
1169 *rx_cfg = t3_read_reg(mac->adapter, A_XGM_RX_CFG);
1174 *rx_hash_high = t3_read_reg(mac->adapter, A_XGM_RX_HASH_HIGH);
1177 *rx_hash_low = t3_read_reg(mac->adapter, A_XGM_RX_HASH_LOW);
1223 status = t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset);
1280 link_fault = t3_read_reg(adapter,
1402 unsigned int status = t3_read_reg(adapter, reg) & mask;
1541 if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR)
1543 t3_read_reg(adapter, A_PCIE_PEX_ERR));
1757 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);
1763 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR),
1764 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0),
1765 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1),
1766 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2));
1773 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR),
1774 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0),
1775 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1),
1776 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2));
1789 addr = t3_read_reg(adapter,
1816 u32 cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset) &
1859 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1888 u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0);
1934 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1998 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
2011 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
2053 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
2085 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */
2102 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */
2119 t3_read_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx)); /* flush */
2214 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2255 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2296 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2333 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2360 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2384 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2408 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2432 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2461 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2481 return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0));
2499 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2507 data[0] = t3_read_reg(adapter, A_SG_CONTEXT_DATA0);
2508 data[1] = t3_read_reg(adapter, A_SG_CONTEXT_DATA1);
2509 data[2] = t3_read_reg(adapter, A_SG_CONTEXT_DATA2);
2510 data[3] = t3_read_reg(adapter, A_SG_CONTEXT_DATA3);
2635 val = t3_read_reg(adapter, A_TP_RSS_LKP_TABLE);
2646 val = t3_read_reg(adapter, A_TP_RSS_MAP_TABLE);
2878 val = t3_read_reg(adap, A_TP_PARA_REG3);
3035 val = t3_read_reg(adap, A_TP_MTU_TABLE);
3057 incr[mtu][w] = t3_read_reg(adap, A_TP_CCTRL_TABLE) &
3158 t3_read_reg(adapter, A_TP_PIO_DATA);
3196 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3276 t3_read_reg(adapter, A_XGM_XAUI_IMP);
3278 v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
3329 t3_read_reg(adapter, addr); /* flush */
3330 if (!(t3_read_reg(adapter, addr) & F_BUSY))
3357 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3363 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3368 t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
3370 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
3386 t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3421 t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */
3429 t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */
3434 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
3487 fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
3489 G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
3578 t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3583 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
3619 pci_mode = t3_read_reg(adapter, A_PCIX_MODE);
3684 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3726 t3_read_reg(adapter, A_XGM_PORT_CFG);
3730 t3_read_reg(adapter, A_XGM_PORT_CFG);
3732 t3_read_reg(adapter, A_XGM_PORT_CFG);
3769 if (t3_read_reg(adap, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
3811 adapter->params.rev = t3_read_reg(adapter, A_PL_REV);