Lines Matching defs:t3_set_reg_field
92 * t3_set_reg_field - set a register field to a value
101 void t3_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
216 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
235 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
259 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0);
1170 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG,
1188 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG,
1369 t3_set_reg_field(adapter, A_TP_OUT_CONFIG,
1838 t3_set_reg_field(adap,
2664 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE,
2721 t3_set_reg_field(adap, A_TP_PARA_REG3, V_TXDATAACKIDX(M_TXDATAACKIDX),
2774 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO,
2778 t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
2782 t3_set_reg_field(adap, A_TP_PC_CONFIG,
2786 t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL,
2794 t3_set_reg_field(adap, A_TP_PARA_REG3, F_TXPACEAUTO,
2796 t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
2797 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEAUTOSTRICT);
2799 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
2802 t3_set_reg_field(adap, A_TP_PC_CONFIG,
3230 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE | F_PORT0ACTIVE,
3244 t3_set_reg_field(adap, A_ULPRX_CTL, F_ROUND_ROBIN, 0);
3245 t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0);
3252 t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN);
3253 t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB);
3260 t3_set_reg_field(adap, A_TP_PC_CONFIG, 0, F_TXTOSQUEUEMAPMODE);
3290 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
3301 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALRESET, 0);
3302 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0,
3304 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
3306 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALUPDATE, 0);
3307 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_CALUPDATE);
3389 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB,
3402 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLRST, 0);
3442 t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY);
3497 t3_set_reg_field(adap, A_PCIE_PEX_CTRL1,
3501 t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_ACKLAT(M_ACKLAT),
3504 t3_set_reg_field(adap, A_PCIE_PEX_CTRL0, V_REPLAYLMT(M_REPLAYLMT),
3508 t3_set_reg_field(adap, A_PCIE_CFG, 0,
3560 t3_set_reg_field(adapter, A_PCIX_CFG, 0,
3564 t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0,
3704 t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset,
3927 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,