Lines Matching refs:MDIO_MMD_PMAPMD
118 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL_I2C_CTRL,
125 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_STAT, &stat);
129 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_DATA,
145 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, !!enable);
148 MDIO_MMD_PMAPMD, MDIO_CTRL1,
158 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL100X_TX_CONFIG1, 1)) ||
159 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_HI, 0)) ||
160 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_LO, 0)) ||
161 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_XFI_EQL, 0x18)) ||
162 (err = t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL1002_LB_EN,
181 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
224 return t3_phy_reset(phy, MDIO_MMD_PMAPMD, wait);
296 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 },
297 { MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a },
298 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 },
317 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
328 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 },
332 { MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 },
333 { MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 },
353 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
366 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, &stat);
378 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x200);
384 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x100);
390 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0xd00);
397 { MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 },
398 { MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 },
399 { MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 },
400 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },
401 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8100 },
402 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },
403 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 },
407 { MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 },
408 { MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 },
415 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
420 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 0);
459 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_STAT, &stat);
464 ret = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL,
516 return t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL_OPT_SETTINGS, 0,
527 { MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a },
530 { MDIO_MMD_PMAPMD, 0xcb1b, 0xffff, 0x0200 },
531 { MDIO_MMD_PMAPMD, 0xcb1c, 0xffff, 0x00f0 },
532 { MDIO_MMD_PMAPMD, 0xcc06, 0xffff, 0x00e0 },
555 { MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 },
556 { MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 },
562 { MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 },
568 { MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 },
569 { MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 },
591 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
609 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_STAT, &stat);
629 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT,
631 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
635 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
669 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
673 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
700 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
706 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 },
709 { MDIO_MMD_PMAPMD, 0xcd40, 0xffff, 0x0001 },
712 { MDIO_MMD_PMAPMD, 0xff02, 0xffff, 0x0023 },
713 { MDIO_MMD_PMAPMD, 0xff03, 0xffff, 0x0000 },
714 { MDIO_MMD_PMAPMD, 0xff04, 0xffff, 0x0000 },
728 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
733 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 125);
770 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
839 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
884 !t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &stat) &&