Lines Matching refs:must
562 /* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must
586 * bit high. TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if
793 this value*64B. must be
801 * writing N means that all desc up to *but* excluding N are available. N must
830 * this interrupt to reduce the # of times it must update the
962 * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should
975 * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI
1019 * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set
1085 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access
1131 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg
1324 /* to ensure proper operation, CFG_EN must be cleared to 0 and a delay
1486 clock selection must be
1569 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
1899 #define PCS_CFG_EN 0x01 /* enable PCS. must be
2506 * RX DESC and COMP rings must be 8KB aligned
2507 * TX DESC must be 2KB aligned.
2519 #error TX_DESC_RING_INDEX must be between 0 and 8
2523 #error RX_DESC_RING_INDEX must be between 0 and 8
2527 #error RX_COMP_RING_INDEX must be between 0 and 8
2567 value must be
2574 must be > 8 */
2697 * TX DESC, RX DESC, and RX COMP must each be 8K aligned.
2698 * TX COMPWB must be 8-byte aligned.
2771 /* N_TX_RINGS must be >= N_RX_DESC_RINGS */