Lines Matching defs:stat
978 u32 stat, state_machine;
985 stat = readl(cp->regs + REG_PCS_MII_STATUS);
986 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
987 stat = readl(cp->regs + REG_PCS_MII_STATUS);
992 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
999 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1001 stat |= PCS_MII_STATUS_LINK_STATUS;
1004 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1040 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1041 if (stat == 0x03)
1063 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1065 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1406 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1408 if (!stat)
1411 netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
1415 if (stat & MAC_RX_ALIGN_ERR)
1418 if (stat & MAC_RX_CRC_ERR)
1421 if (stat & MAC_RX_LEN_ERR)
1424 if (stat & MAC_RX_OVERFLOW) {
1439 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1441 if (!stat)
1445 "mac interrupt, stat: 0x%x\n", stat);
1451 if (stat & MAC_CTRL_PAUSE_STATE)
1454 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1455 cp->pause_last_time_recvd = (stat >> 16);
1578 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1582 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1585 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1592 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1594 if (!stat)
1598 stat, readl(cp->regs + REG_BIM_DIAG));
1601 if ((stat & PCI_ERR_BADACK) &&
1605 if (stat & PCI_ERR_DTRTO)
1607 if (stat & PCI_ERR_OTHER)
1609 if (stat & PCI_ERR_BIM_DMA_WRITE)
1611 if (stat & PCI_ERR_BIM_DMA_READ)
1615 if (stat & PCI_ERR_OTHER) {