net/can/bfin_can.c

82 	bfin_write16(&reg->clock, clk);
83 	bfin_write16(&reg->timing, timing);
99 	bfin_write16(&reg->mbim1, 0);
100 	bfin_write16(&reg->mbim2, 0);
101 	bfin_write16(&reg->gim, 0);
104 	bfin_write16(&reg->control, SRS | CCR);
106 	bfin_write16(&reg->control, CCR);
122 	bfin_write16(&reg->mc1, 0);
123 	bfin_write16(&reg->mc2, 0);
126 	bfin_write16(&reg->md1, 0xFFFF);   /* mailbox 1-16 are RX */
127 	bfin_write16(&reg->md2, 0);   /* mailbox 17-32 are TX */
131 		bfin_write16(&reg->chl[RECEIVE_STD_CHL + i].id0, 0);
132 		bfin_write16(&reg->chl[RECEIVE_STD_CHL + i].id1, AME);
133 		bfin_write16(&reg->chl[RECEIVE_STD_CHL + i].dlc, 0);
134 		bfin_write16(&reg->msk[RECEIVE_STD_CHL + i].amh, 0x1FFF);
135 		bfin_write16(&reg->msk[RECEIVE_STD_CHL + i].aml, 0xFFFF);
140 		bfin_write16(&reg->chl[RECEIVE_EXT_CHL + i].id0, 0);
141 		bfin_write16(&reg->chl[RECEIVE_EXT_CHL + i].id1, AME | IDE);
142 		bfin_write16(&reg->chl[RECEIVE_EXT_CHL + i].dlc, 0);
143 		bfin_write16(&reg->msk[RECEIVE_EXT_CHL + i].amh, 0x1FFF);
144 		bfin_write16(&reg->msk[RECEIVE_EXT_CHL + i].aml, 0xFFFF);
147 	bfin_write16(&reg->mc2, BIT(TRANSMIT_CHL - 16));
148 	bfin_write16(&reg->mc1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL));
163 	bfin_write16(&reg->control, bfin_read16(&reg->control) & ~CCR);
177 	bfin_write16(&reg->mbtif1, 0xFFFF);
178 	bfin_write16(&reg->mbtif2, 0xFFFF);
179 	bfin_write16(&reg->mbrif1, 0xFFFF);
180 	bfin_write16(&reg->mbrif2, 0xFFFF);
185 	bfin_write16(&reg->gis, 0x7FF); /* overwrites with '1' */
192 	bfin_write16(&reg->mbim1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL));
193 	bfin_write16(&reg->mbim2, BIT(TRANSMIT_CHL - 16));
195 	bfin_write16(&reg->gim, EPIM | BOIM | RMLIM);
245 		bfin_write16(&reg->chl[TRANSMIT_CHL].id0, id);
258 			bfin_write16(&reg->chl[TRANSMIT_CHL].id1,
266 		bfin_write16(&reg->chl[TRANSMIT_CHL].data[i], val);
270 	bfin_write16(&reg->chl[TRANSMIT_CHL].dlc, dlc);
275 	bfin_write16(&reg->trs2, BIT(TRANSMIT_CHL - 16));
424 		bfin_write16(&reg->mbtif2, 0xFFFF);
432 		bfin_write16(&reg->mbrif1, 0xFFFF);
438 		bfin_write16(&reg->gis, 0x7FF);
643 		bfin_write16(&reg->control, bfin_read16(&reg->control) | SMR);
666 		bfin_write16(&reg->intr, 0);