Lines Matching refs:cfspi
26 static inline int forward_to_spi_cmd(struct cfspi *cfspi)
28 return cfspi->rx_cpck_len;
32 static inline int forward_to_spi_cmd(struct cfspi *cfspi)
45 static inline void debugfs_store_prev(struct cfspi *cfspi)
48 cfspi->pcmd = cfspi->cmd;
50 cfspi->tx_ppck_len = cfspi->tx_cpck_len;
51 cfspi->rx_ppck_len = cfspi->rx_cpck_len;
54 static inline void debugfs_store_prev(struct cfspi *cfspi)
61 struct cfspi *cfspi;
65 cfspi = container_of(work, struct cfspi, work);
68 cfspi->cmd = SPI_CMD_EOT;
72 cfspi_dbg_state(cfspi, CFSPI_STATE_WAITING);
75 wait_event_interruptible(cfspi->wait,
76 test_bit(SPI_XFER, &cfspi->state) ||
77 test_bit(SPI_TERMINATE, &cfspi->state));
79 if (test_bit(SPI_TERMINATE, &cfspi->state))
84 memset(cfspi->xfer.va_tx, 0xFF, SPI_DMA_BUF_LEN);
85 memset(cfspi->xfer.va_rx, 0xFF, SPI_DMA_BUF_LEN);
88 cfspi_dbg_state(cfspi, CFSPI_STATE_AWAKE);
91 if (cfspi->tx_cpck_len) {
94 cfspi_dbg_state(cfspi, CFSPI_STATE_FETCH_PKT);
97 ptr = (u8 *) cfspi->xfer.va_tx;
99 len = cfspi_xmitfrm(cfspi, ptr, cfspi->tx_cpck_len);
100 WARN_ON(len != cfspi->tx_cpck_len);
103 cfspi_dbg_state(cfspi, CFSPI_STATE_GET_NEXT);
106 cfspi->tx_npck_len = cfspi_xmitlen(cfspi);
108 WARN_ON(cfspi->tx_npck_len > SPI_DMA_BUF_LEN);
114 ptr = (u8 *) cfspi->xfer.va_tx;
117 *ptr++ = cfspi->tx_npck_len & 0x00FF;
118 *ptr++ = (cfspi->tx_npck_len & 0xFF00) >> 8;
121 cfspi->xfer.tx_dma_len = cfspi->tx_cpck_len + SPI_IND_SZ;
122 cfspi->xfer.rx_dma_len = cfspi->rx_cpck_len + SPI_CMD_SZ;
125 if (cfspi->tx_cpck_len &&
126 (cfspi->xfer.tx_dma_len % spi_frm_align)) {
128 cfspi->xfer.tx_dma_len += spi_frm_align -
129 (cfspi->xfer.tx_dma_len % spi_frm_align);
133 if (cfspi->rx_cpck_len &&
134 (cfspi->xfer.rx_dma_len % spi_frm_align)) {
136 cfspi->xfer.rx_dma_len += spi_frm_align -
137 (cfspi->xfer.rx_dma_len % spi_frm_align);
140 cfspi_dbg_state(cfspi, CFSPI_STATE_INIT_XFER);
143 ret = cfspi->dev->init_xfer(&cfspi->xfer, cfspi->dev);
146 cfspi_dbg_state(cfspi, CFSPI_STATE_WAIT_ACTIVE);
154 cfspi_dbg_state(cfspi, CFSPI_STATE_SIG_ACTIVE);
157 cfspi->dev->sig_xfer(true, cfspi->dev);
159 cfspi_dbg_state(cfspi, CFSPI_STATE_WAIT_XFER_DONE);
162 wait_for_completion(&cfspi->comp);
164 cfspi_dbg_state(cfspi, CFSPI_STATE_XFER_DONE);
166 if (cfspi->cmd == SPI_CMD_EOT) {
171 clear_bit(SPI_SS_ON, &cfspi->state);
174 cfspi_dbg_state(cfspi, CFSPI_STATE_WAIT_INACTIVE);
177 if (SPI_XFER_TIME_USEC(cfspi->xfer.tx_dma_len,
178 cfspi->dev->clk_mhz) <
183 (cfspi->xfer.tx_dma_len, cfspi->dev->clk_mhz));
186 cfspi_dbg_state(cfspi, CFSPI_STATE_SIG_INACTIVE);
189 cfspi->dev->sig_xfer(false, cfspi->dev);
192 if (cfspi->rx_cpck_len) {
195 cfspi_dbg_state(cfspi, CFSPI_STATE_DELIVER_PKT);
198 ptr = ((u8 *)(cfspi->xfer.va_rx + SPI_DATA_POS));
200 len = cfspi_rxfrm(cfspi, ptr, cfspi->rx_cpck_len);
201 WARN_ON(len != cfspi->rx_cpck_len);
205 ptr = (u8 *) cfspi->xfer.va_rx;
207 ptr += forward_to_spi_cmd(cfspi);
209 cfspi->cmd = *ptr++;
210 cfspi->cmd |= ((*ptr++) << 8) & 0xFF00;
211 cfspi->rx_npck_len = *ptr++;
212 cfspi->rx_npck_len |= ((*ptr++) << 8) & 0xFF00;
214 WARN_ON(cfspi->rx_npck_len > SPI_DMA_BUF_LEN);
215 WARN_ON(cfspi->cmd > SPI_CMD_EOT);
217 debugfs_store_prev(cfspi);
220 if (cfspi->cmd == SPI_CMD_EOT) {
222 cfspi->tx_cpck_len = 0;
223 cfspi->rx_cpck_len = 0;
226 cfspi->tx_cpck_len = cfspi->tx_npck_len;
227 cfspi->rx_cpck_len = cfspi->rx_npck_len;
236 spin_lock_irqsave(&cfspi->lock, flags);
237 if (cfspi->cmd == SPI_CMD_EOT && !cfspi_xmitlen(cfspi)
238 && !test_bit(SPI_SS_ON, &cfspi->state))
239 clear_bit(SPI_XFER, &cfspi->state);
241 spin_unlock_irqrestore(&cfspi->lock, flags);