Lines Matching refs:write_reg_high
277 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
305 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE); /* Enable Tx and Rx. */
314 write_reg_high(ioaddr, CMR1, CMR1h_TxRxOFF); /* Disable Tx and Rx units. */
332 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
402 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_LOW);
403 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_HIGH);
408 write_reg_high(ioaddr, PROM_CMD, EE_CLK_LOW & ~EE_CS);
458 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
463 write_reg_high(ioaddr, CMR2, lp->addr_mode);
471 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
478 write_reg_high(ioaddr, IMR, ISRh_RxErr);
564 write_reg_high(ioaddr, IMR, 0);
579 write_reg_high(ioaddr, IMR, ISRh_RxErr);
626 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
629 write_reg_high(ioaddr, ISR, ISRh_RxErr);
630 write_reg_high(ioaddr, CMR2, lp->addr_mode);
695 write_reg_high(ioaddr, IMR, ISRh_RxErr); /* Hmmm, really needed? */
748 write_reg_high(ioaddr, CMR1, CMR1h_TxENABLE);
749 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
813 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
820 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
837 write_reg_high(ioaddr, CMR2, lp->addr_mode);
877 write_reg_high(ioaddr, CMR2, lp->addr_mode);