Lines Matching refs:hw
251 * hw - Struct containing variables accessed by shared code
254 static s32 atl1_reset_hw(struct atl1_hw *hw)
256 struct pci_dev *pdev = hw->back->pdev;
257 struct atl1_adapter *adapter = hw->back;
266 * iowrite32(0, hw->hw_addr + REG_IMR);
267 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
276 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
277 ioread32(hw->hw_addr + REG_MASTER_CTRL);
279 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
280 ioread16(hw->hw_addr + REG_PHY_ENABLE);
287 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
309 static int atl1_check_eeprom_exist(struct atl1_hw *hw)
312 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
315 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
318 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
322 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
331 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
333 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
334 ioread32(hw->hw_addr + REG_VPD_CAP);
338 control = ioread32(hw->hw_addr + REG_VPD_CAP);
343 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
352 * hw - Struct containing variables accessed by shared code
355 s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
363 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
364 ioread32(hw->hw_addr + REG_MDIO_CTRL);
368 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
385 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
390 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
391 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
406 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
409 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
410 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
414 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
422 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
431 static int atl1_get_permanent_address(struct atl1_hw *hw)
439 if (is_valid_ether_addr(hw->perm_mac_addr))
445 if (!atl1_check_eeprom_exist(hw)) {
451 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
472 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
483 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
505 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
515 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
516 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
520 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
529 * hw - Struct containing variables accessed by shared code
531 static s32 atl1_read_mac_addr(struct atl1_hw *hw)
535 if (atl1_get_permanent_address(hw))
536 random_ether_addr(hw->perm_mac_addr);
539 hw->mac_addr[i] = hw->perm_mac_addr[i];
545 * hw - Struct containing variables accessed by shared code
555 u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
569 * hw - Struct containing variables accessed by shared code
572 void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
588 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
590 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
595 * hw - Struct containing variables accessed by shared code
599 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
608 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
609 ioread32(hw->hw_addr + REG_MDIO_CTRL);
613 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
626 * hw - Struct containing variables accessed by shared code
630 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
633 ret = atl1_write_phy_reg(hw, 29, 0x0029);
636 return atl1_write_phy_reg(hw, 30, 0);
641 * hw - Struct containing variables accessed by shared code
645 static s32 atl1_phy_reset(struct atl1_hw *hw)
647 struct pci_dev *pdev = hw->back->pdev;
648 struct atl1_adapter *adapter = hw->back;
652 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
653 hw->media_type == MEDIA_TYPE_1000M_FULL)
656 switch (hw->media_type) {
676 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
686 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
703 * hw - Struct containing variables accessed by shared code
705 static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
729 switch (hw->media_type) {
762 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
763 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
765 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
769 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
778 * hw - Struct containing variables accessed by shared code
782 static s32 atl1_setup_link(struct atl1_hw *hw)
784 struct pci_dev *pdev = hw->back->pdev;
785 struct atl1_adapter *adapter = hw->back;
794 ret_val = atl1_phy_setup_autoneg_adv(hw);
802 ret_val = atl1_phy_reset(hw);
808 hw->phy_configured = true;
812 static void atl1_init_flash_opcode(struct atl1_hw *hw)
814 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
816 hw->flash_vendor = 0;
819 iowrite8(flash_table[hw->flash_vendor].cmd_program,
820 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
821 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
822 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
823 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
824 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
825 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
826 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
827 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
828 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
829 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
830 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
831 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
832 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
833 iowrite8(flash_table[hw->flash_vendor].cmd_read,
834 hw->hw_addr + REG_SPI_FLASH_OP_READ);
839 * hw - Struct containing variables accessed by shared code
845 static s32 atl1_init_hw(struct atl1_hw *hw)
850 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
852 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
854 atl1_init_flash_opcode(hw);
856 if (!hw->phy_configured) {
858 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
862 ret_val = atl1_phy_leave_power_saving(hw);
866 ret_val = atl1_setup_link(hw);
873 * hw - Struct containing variables accessed by shared code
877 static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
879 struct pci_dev *pdev = hw->back->pdev;
880 struct atl1_adapter *adapter = hw->back;
885 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
916 void atl1_set_mac_addr(struct atl1_hw *hw)
924 value = (((u32) hw->mac_addr[2]) << 24) |
925 (((u32) hw->mac_addr[3]) << 16) |
926 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
927 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
929 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
930 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
943 struct atl1_hw *hw = &adapter->hw;
946 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
947 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
950 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
955 hw->phy_configured = false;
956 hw->preamble_len = 7;
957 hw->ipgt = 0x60;
958 hw->min_ifg = 0x50;
959 hw->ipgr1 = 0x40;
960 hw->ipgr2 = 0x60;
961 hw->max_retry = 0xf;
962 hw->lcol = 0x37;
963 hw->jam_ipg = 7;
964 hw->rfd_burst = 8;
965 hw->rrd_burst = 8;
966 hw->rfd_fetch_gap = 1;
967 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
968 hw->rx_jumbo_lkah = 1;
969 hw->rrd_ret_timer = 16;
970 hw->tpd_burst = 4;
971 hw->tpd_fetch_th = 16;
972 hw->txf_burst = 0x100;
973 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
974 hw->tpd_fetch_gap = 1;
975 hw->rcb_value = atl1_rcb_64;
976 hw->dma_ord = atl1_dma_ord_enh;
977 hw->dmar_block = atl1_dma_req_256;
978 hw->dmaw_block = atl1_dma_req_256;
979 hw->cmb_rrd = 4;
980 hw->cmb_tpd = 4;
981 hw->cmb_rx_timer = 1; /* about 2us */
982 hw->cmb_tx_timer = 1; /* about 2us */
983 hw->smb_timer = 100000; /* about 200ms */
996 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
1006 atl1_write_phy_reg(&adapter->hw, reg_num, val);
1264 struct atl1_hw *hw = &adapter->hw;
1280 value |= (((u32) adapter->hw.preamble_len
1296 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1301 struct atl1_hw *hw = &adapter->hw;
1308 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1309 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1323 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1327 switch (hw->media_type) {
1378 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1379 hw->media_type != MEDIA_TYPE_1000M_FULL) {
1380 switch (hw->media_type) {
1397 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
1424 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1434 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1437 static void set_flow_ctrl_new(struct atl1_hw *hw)
1442 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1451 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1454 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1463 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1474 struct atl1_hw *hw = &adapter->hw;
1478 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1481 value = (((u32) hw->mac_addr[2]) << 24) |
1482 (((u32) hw->mac_addr[3]) << 16) |
1483 (((u32) hw->mac_addr[4]) << 8) |
1484 (((u32) hw->mac_addr[5]));
1485 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1486 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1487 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1493 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1496 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1498 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1500 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1502 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1504 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
1510 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1511 iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1515 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
1524 iowrite32(value, hw->hw_addr + REG_MAILBOX);
1527 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1529 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1531 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1533 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1535 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1538 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1539 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1543 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1545 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1548 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1549 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
1552 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
1554 /* set max frame size hw will accept */
1555 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
1558 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1560 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1562 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1564 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1567 switch (hw->dev_rev) {
1575 set_flow_ctrl_new(hw);
1580 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1582 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1584 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1587 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1590 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1592 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1594 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1597 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1599 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1601 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1604 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1607 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1609 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1612 value |= (u32) hw->dma_ord;
1613 if (atl1_rcb_128 == hw->rcb_value)
1615 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1618 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1619 hw->cmb_tpd : adapter->tpd_ring.count;
1621 value |= hw->cmb_rrd;
1622 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1623 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1624 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1625 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
1629 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1631 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1638 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1639 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1652 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1654 value = ioread32(adapter->hw.hw_addr + 0x1008);
1656 iowrite32(value, adapter->hw.hw_addr + 0x1008);
1669 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1672 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
1687 smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
1767 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2057 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2464 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
2476 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2488 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2524 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
2536 struct atl1_hw *hw = &adapter->hw;
2541 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
2542 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
2543 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
2561 ret = atl1_reset_hw(&adapter->hw);
2564 return atl1_init_hw(&adapter->hw);
2623 atl1_reset_hw(&adapter->hw);
2666 adapter->hw.max_frame_size = max_frame;
2667 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
2669 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
2739 struct atl1_hw *hw = &adapter->hw;
2755 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2756 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2762 val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
2775 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2776 ioread32(hw->hw_addr + REG_WOL_CTRL);
2784 ctrl |= (((u32)adapter->hw.preamble_len &
2790 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2791 ioread32(hw->hw_addr + REG_MAC_CTRL);
2794 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2796 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2797 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2805 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2806 ioread32(hw->hw_addr + REG_WOL_CTRL);
2807 iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
2808 ioread32(hw->hw_addr + REG_MAC_CTRL);
2809 hw->phy_configured = false;
2815 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2816 ioread32(hw->hw_addr + REG_WOL_CTRL);
2817 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2819 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2820 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2821 hw->phy_configured = false;
2850 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
2854 atl1_reset_hw(&adapter->hw);
2964 adapter->hw.back = adapter;
2967 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2968 if (!adapter->hw.hw_addr) {
2973 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
3011 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3017 if (atl1_reset_hw(&adapter->hw)) {
3023 atl1_read_mac_addr(&adapter->hw);
3024 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
3034 err = atl1_init_hw(&adapter->hw);
3064 pci_iounmap(pdev, adapter->hw.hw_addr);
3099 if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
3100 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
3102 atl1_set_mac_addr(&adapter->hw);
3105 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3107 pci_iounmap(pdev, adapter->hw.hw_addr);
3218 struct atl1_hw *hw = &adapter->hw;
3227 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3228 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3230 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
3247 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
3257 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3258 hw->media_type == MEDIA_TYPE_1000M_FULL)
3270 struct atl1_hw *hw = &adapter->hw;
3273 u16 old_media_type = hw->media_type;
3283 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
3293 hw->media_type = MEDIA_TYPE_1000M_FULL;
3296 hw->media_type = MEDIA_TYPE_100M_FULL;
3298 hw->media_type = MEDIA_TYPE_100M_HALF;
3301 hw->media_type = MEDIA_TYPE_10M_FULL;
3303 hw->media_type = MEDIA_TYPE_10M_HALF;
3306 switch (hw->media_type) {
3325 if (atl1_phy_setup_autoneg_adv(hw)) {
3332 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3333 hw->media_type == MEDIA_TYPE_1000M_FULL)
3336 switch (hw->media_type) {
3355 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3358 hw->media_type = old_media_type;
3434 struct atl1_hw *hw = &adapter->hw;
3471 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
3580 struct atl1_hw *hw = &adapter->hw;
3582 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3583 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3596 struct atl1_hw *hw = &adapter->hw;
3598 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3599 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3636 struct atl1_hw *hw = &adapter->hw;
3642 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3643 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3646 switch (hw->media_type) {
3663 atl1_write_phy_reg(hw, MII_BMCR, phy_data);