Lines Matching refs:hw
99 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
100 AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
101 AT_WRITE_FLUSH(&adapter->hw);
112 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
113 AT_WRITE_FLUSH(&adapter->hw);
124 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
125 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
126 AT_WRITE_FLUSH(&adapter->hw);
136 struct atl1e_hw *hw = &adapter->hw;
140 atl1e_restart_autoneg(hw);
165 struct atl1e_hw *hw = &adapter->hw;
171 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
172 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
178 value = AT_READ_REG(hw, REG_MAC_CTRL);
180 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
187 err = atl1e_get_speed_and_duplex(hw, &speed, &duplex);
235 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
236 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
286 struct atl1e_hw *hw = &adapter->hw;
292 mac_ctrl_data = AT_READ_REG(hw, REG_MAC_CTRL);
303 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
306 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
307 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
311 hash_value = atl1e_hash_mc_addr(hw, ha->addr);
312 atl1e_hash_set(hw, hash_value);
327 mac_ctrl_data = AT_READ_REG(&adapter->hw, REG_MAC_CTRL);
337 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
365 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
367 atl1e_hw_set_mac_addr(&adapter->hw);
395 adapter->hw.max_frame_size = new_mtu;
396 adapter->hw.rx_jumbo_th = (max_frame + 7) >> 3;
412 atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
421 atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
448 if (atl1e_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
463 if (atl1e_write_phy_reg(&adapter->hw,
536 struct atl1e_hw *hw = &adapter->hw;
546 hw->vendor_id = pdev->vendor;
547 hw->device_id = pdev->device;
548 hw->subsystem_vendor_id = pdev->subsystem_vendor;
549 hw->subsystem_id = pdev->subsystem_device;
551 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
552 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
554 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
556 if (hw->revision_id >= 0xF0) {
557 hw->nic_type = athr_l2e_revB;
560 hw->nic_type = athr_l1e;
562 hw->nic_type = athr_l2e_revA;
565 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
568 hw->emi_ca = true;
570 hw->emi_ca = false;
572 hw->phy_configured = false;
573 hw->preamble_len = 7;
574 hw->max_frame_size = adapter->netdev->mtu;
575 hw->rx_jumbo_th = (hw->max_frame_size + ETH_HLEN +
578 hw->rrs_type = atl1e_rrs_disable;
579 hw->indirect_tab = 0;
580 hw->base_cpu = 0;
584 hw->ict = 50000; /* 100ms */
585 hw->smb_timer = 200000; /* 200ms */
586 hw->tpd_burst = 5;
587 hw->rrd_thresh = 1;
588 hw->tpd_thresh = adapter->tx_ring.count / 2;
589 hw->rx_count_down = 4; /* 2us resolution */
590 hw->tx_count_down = hw->imt * 4 / 3;
591 hw->dmar_block = atl1e_dma_req_1024;
592 hw->dmaw_block = atl1e_dma_req_1024;
593 hw->dmar_dly_cnt = 15;
594 hw->dmaw_dly_cnt = 4;
701 + adapter->hw.max_frame_size
865 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
873 AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
875 AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO,
877 AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
878 AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO,
884 AT_WRITE_REG(hw, atl1e_rx_page_hi_addr_regs[i],
895 AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[i][j],
897 AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[i][j],
899 AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[i][j], 1);
903 AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
905 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
910 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
917 if (hw->nic_type != athr_l2e_revB) {
919 if (hw->max_frame_size <= 1500) {
920 jumbo_thresh = hw->max_frame_size + extra_size;
921 } else if (hw->max_frame_size < 6*1024) {
923 (hw->max_frame_size + extra_size) * 2 / 3;
925 jumbo_thresh = (hw->max_frame_size + extra_size) / 2;
927 AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
930 dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
935 hw->dmaw_block = min(max_pay_load, hw->dmaw_block);
939 hw->dmar_block = min(max_pay_load, hw->dmar_block);
941 if (hw->nic_type != athr_l2e_revB)
942 AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2,
943 atl1e_pay_load_size[hw->dmar_block]);
945 AT_WRITE_REGW(hw, REG_TXQ_CTRL,
946 (((u16)hw->tpd_burst & TXQ_CTRL_NUM_TPD_BURST_MASK)
953 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
960 if (hw->nic_type != athr_l2e_revB) {
961 AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM,
962 (u16)((hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) <<
967 rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
975 AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);
979 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
980 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
982 if (hw->rrs_type & atl1e_rrs_ipv4)
985 if (hw->rrs_type & atl1e_rrs_ipv4_tcp)
988 if (hw->rrs_type & atl1e_rrs_ipv6)
991 if (hw->rrs_type & atl1e_rrs_ipv6_tcp)
994 if (hw->rrs_type != atl1e_rrs_disable)
1001 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1006 struct atl1e_hw *hw = &adapter->hw;
1010 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1012 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1015 dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
1017 dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
1020 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1026 struct atl1e_hw *hw = &adapter->hw;
1042 value |= (((u32)adapter->hw.preamble_len &
1054 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
1065 struct atl1e_hw *hw = &adapter->hw;
1070 AT_WRITE_REG(hw, REG_ISR, ~0);
1073 atl1e_hw_set_mac_addr(hw);
1078 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1086 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, hw->imt);
1087 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, hw->imt);
1088 AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE |
1092 AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, hw->rrd_thresh);
1093 AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, hw->tpd_thresh);
1094 AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, hw->rx_count_down);
1095 AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, hw->tx_count_down);
1098 AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, hw->ict);
1101 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1114 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, hw->smb_timer);
1116 intr_status_data = AT_READ_REG(hw, REG_ISR);
1123 AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
1178 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1186 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1197 atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data);
1206 u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX);
1250 struct atl1e_hw *hw = &adapter->hw;
1256 status = AT_READ_REG(hw, REG_ISR);
1267 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1311 AT_WRITE_REG(hw, REG_IMR,
1313 AT_WRITE_FLUSH(hw);
1320 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1396 AT_WRITE_REG(&adapter->hw, REG_DEBUG_DATA0,
1461 AT_WRITE_REGB(&adapter->hw, reg_addr, 1);
1497 imr_data = AT_READ_REG(&adapter->hw, REG_IMR);
1498 AT_WRITE_REG(&adapter->hw, REG_IMR, imr_data | ISR_RX_EVENT);
1784 AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
1897 err = atl1e_init_hw(&adapter->hw);
1914 val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1915 AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
1937 atl1e_reset_hw(&adapter->hw);
1992 atl1e_reset_hw(&adapter->hw);
2024 struct atl1e_hw *hw = &adapter->hw;
2051 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2052 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2056 if ((atl1e_write_phy_reg(hw, MII_AT001_CR, 0) != 0) ||
2057 (atl1e_write_phy_reg(hw,
2059 (atl1e_phy_commit(hw)) != 0) {
2064 hw->phy_configured = false; /* re-init PHY when resume */
2075 atl1e_read_phy_reg(hw, MII_BMSR,
2087 if (atl1e_write_phy_reg(hw, MII_INT_CTRL, 0x400) != 0) {
2094 atl1e_read_phy_reg(hw, MII_INT_STATUS, &mii_intr_status_data);
2099 mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
2113 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2114 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2116 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2118 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2125 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2128 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2130 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2132 atl1e_force_ps(hw);
2133 hw->phy_configured = false; /* re-init PHY when resume */
2168 AT_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
2173 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
2181 atl1e_reset_hw(&adapter->hw);
2300 adapter->hw.adapter = adapter;
2301 adapter->hw.hw_addr = pci_iomap(pdev, BAR_0, 0);
2302 if (!adapter->hw.hw_addr) {
2307 netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
2339 atl1e_phy_init(&adapter->hw);
2342 err = atl1e_reset_hw(&adapter->hw);
2348 if (atl1e_read_mac_addr(&adapter->hw) != 0) {
2354 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2355 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
2356 netdev_dbg(netdev, "mac address : %pM\n", adapter->hw.mac_addr);
2378 iounmap(adapter->hw.hw_addr);
2415 atl1e_force_ps(&adapter->hw);
2416 iounmap(adapter->hw.hw_addr);
2472 atl1e_reset_hw(&adapter->hw);