Lines Matching refs:hw
32 int atl1e_check_eeprom_exist(struct atl1e_hw *hw)
36 value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
39 AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
41 value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST);
45 void atl1e_hw_set_mac_addr(struct atl1e_hw *hw)
53 value = (((u32)hw->mac_addr[2]) << 24) |
54 (((u32)hw->mac_addr[3]) << 16) |
55 (((u32)hw->mac_addr[4]) << 8) |
56 (((u32)hw->mac_addr[5])) ;
57 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
59 value = (((u32)hw->mac_addr[0]) << 8) |
60 (((u32)hw->mac_addr[1])) ;
61 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
68 static int atl1e_get_permanent_address(struct atl1e_hw *hw)
75 if (is_valid_ether_addr(hw->perm_mac_addr))
81 if (!atl1e_check_eeprom_exist(hw)) {
83 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
85 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
88 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
97 addr[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
98 addr[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4);
103 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
110 bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value)
115 bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value)
123 AT_WRITE_REG(hw, REG_VPD_DATA, 0);
125 AT_WRITE_REG(hw, REG_VPD_CAP, control);
129 control = AT_READ_REG(hw, REG_VPD_CAP);
134 *p_value = AT_READ_REG(hw, REG_VPD_DATA);
140 void atl1e_force_ps(struct atl1e_hw *hw)
142 AT_WRITE_REGW(hw, REG_GPHY_CTRL,
149 * hw - Struct containing variables accessed by shared code
151 int atl1e_read_mac_addr(struct atl1e_hw *hw)
155 err = atl1e_get_permanent_address(hw);
158 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
167 u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr)
182 * hw - Struct containing variables accessed by shared code
185 void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value)
202 mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
206 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
210 * hw - Struct containing variables accessed by shared code
213 int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data)
222 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
228 val = AT_READ_REG(hw, REG_MDIO_CTRL);
243 * hw - Struct containing variables accessed by shared code
247 int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
258 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
263 val = AT_READ_REG(hw, REG_MDIO_CTRL);
278 static void atl1e_init_pcie(struct atl1e_hw *hw)
283 AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
287 value = AT_READ_REG(hw, 0x1008);
289 AT_WRITE_REG(hw, 0x1008, value);
294 * hw - Struct containing variables accessed by shared code
296 static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
302 if (0 != hw->mii_autoneg_adv_reg)
328 switch (hw->media_type) {
334 hw->autoneg_advertised = ADVERTISE_10_HALF |
338 if (hw->nic_type == athr_l1e) {
341 hw->autoneg_advertised |= ADVERTISE_1000_FULL;
347 hw->autoneg_advertised = ADVERTISE_100_FULL;
352 hw->autoneg_advertised = ADVERTISE_100_HALF;
357 hw->autoneg_advertised = ADVERTISE_10_FULL;
362 hw->autoneg_advertised = ADVERTISE_10_HALF;
369 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
370 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
372 ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
376 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
377 ret_val = atl1e_write_phy_reg(hw, MII_AT001_CR,
390 * hw - Struct containing variables accessed by shared code
394 int atl1e_phy_commit(struct atl1e_hw *hw)
396 struct atl1e_adapter *adapter = hw->adapter;
402 ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data);
411 val = AT_READ_REG(hw, REG_MDIO_CTRL);
427 int atl1e_phy_init(struct atl1e_hw *hw)
429 struct atl1e_adapter *adapter = hw->adapter;
433 if (hw->phy_configured) {
434 if (hw->re_autoneg) {
435 hw->re_autoneg = false;
436 return atl1e_restart_autoneg(hw);
442 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
444 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
450 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB);
453 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00);
457 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0);
462 /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */
463 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val);
467 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12);
470 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04);
474 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4);
477 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB);
481 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5);
484 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46);
491 ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00);
498 ret_val = atl1e_phy_setup_autoneg_adv(hw);
506 ret_val = atl1e_phy_commit(hw);
512 hw->phy_configured = true;
519 * hw - Struct containing variables accessed by shared code
522 int atl1e_reset_hw(struct atl1e_hw *hw)
524 struct atl1e_adapter *adapter = hw->adapter;
546 AT_WRITE_REG(hw, REG_MASTER_CTRL,
553 idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS);
573 * hw - Struct containing variables accessed by shared code
579 int atl1e_init_hw(struct atl1e_hw *hw)
583 atl1e_init_pcie(hw);
587 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
588 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
590 ret_val = atl1e_phy_init(hw);
598 * hw - Struct containing variables accessed by shared code
602 int atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex)
608 err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
638 int atl1e_restart_autoneg(struct atl1e_hw *hw)
642 err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
646 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
647 err = atl1e_write_phy_reg(hw, MII_AT001_CR,
648 hw->mii_1000t_ctrl_reg);
653 err = atl1e_write_phy_reg(hw, MII_BMCR,